isa_aarch32.json (423918B)
1 { 2 "instructions": [ 3 {"category": "GP", "data": [ 4 {"inst": "adc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0101|0|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "C=R"}, 5 {"inst": "adc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0101|0|Rn|Rd|n:5|sop:2|0|Rm" , "io": "C=R"}, 6 {"inst": "adc Rd, Rn, #immA" , "a32": "cond|001|0101|0|Rn|Rd|imm:12" , "io": "C=R"}, 7 {"inst": "adcS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0101|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=X V=W"}, 8 {"inst": "adcS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0101|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=X V=W"}, 9 {"inst": "adcS Rd!=PC, Rn, #immA" , "a32": "cond|001|0101|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=X V=W"}, 10 {"inst": "add Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0100|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 11 {"inst": "add Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0100|0|Rn|Rd|n:5|sop:2|0|Rm"}, 12 {"inst": "add Rd, Rn!=PC, #immA" , "a32": "cond|001|0100|0|Rn|Rd|imm:12"}, 13 {"inst": "addS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0100|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"}, 14 {"inst": "addS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0100|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"}, 15 {"inst": "addS Rd!=PC, Rn, #immA" , "a32": "cond|001|0100|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"}, 16 {"inst": "adr Rd, #relA" , "a32": "cond|001|0PN0|0|1111|Rd|relA:12"}, 17 {"inst": "and Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0000|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 18 {"inst": "and Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0000|0|Rn|Rd|n:5|sop:2|0|Rm"}, 19 {"inst": "and Rd, Rn, #immA" , "a32": "cond|001|0000|0|Rn|Rd|imm:12"}, 20 {"inst": "andS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0000|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"}, 21 {"inst": "andS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0000|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"}, 22 {"inst": "andS Rd!=PC, Rn, #immA" , "a32": "cond|001|0000|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"}, 23 {"inst": "asr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0101|Rn"}, 24 {"inst": "asr Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|100|Rn"}, 25 {"inst": "asrS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0101|Rn" , "io": "N=W Z=W C=W"}, 26 {"inst": "asrS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|100|Rn" , "io": "N=W Z=W C=W"}, 27 {"inst": "b #relS*4" , "a32": "cond|101|0|relS:24"}, 28 {"inst": "bfc Rd!=PC, #lsb, #width" , "a32": "cond|011|1110|msb:5|Rd|lsb:5|001|1111" , "imm": "BfcBfiImm(lsb, width)"}, 29 {"inst": "bfi Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1110|msb:5|Rd|lsb:5|001|Rn" , "imm": "BfcBfiImm(lsb, width)"}, 30 {"inst": "bic Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1110|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 31 {"inst": "bic Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|1110|0|Rn|Rd|n:5|sop:2|0|Rm"}, 32 {"inst": "bic Rd, Rn, #immA" , "a32": "cond|001|1110|0|Rn|Rd|imm:12"}, 33 {"inst": "bicS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1110|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"}, 34 {"inst": "bicS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|1110|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"}, 35 {"inst": "bicS Rd!=PC, Rn, #immA" , "a32": "cond|001|1110|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"}, 36 {"inst": "bkpt #immZ" , "a32": "cond|000|1001|0|immZ:12|0111|immZ:4"}, 37 {"inst": "bl #relS*4" , "a32": "cond|101|1|relS:24"}, 38 {"inst": "blx Rm!=PC" , "a32": "cond|000|1001|0|1111|1111|1111|0011|Rm"}, 39 {"inst": "blx #relS*2" , "a32": "1111|101|relS[0]|relS[24:1]" }, 40 {"inst": "bx Rm" , "a32": "cond|000|1001|0|1111|1111|1111|0001|Rm"}, 41 {"inst": "bxj Rm!=PC" , "a32": "cond|000|1001|0|1111|1111|1111|0010|Rm"}, 42 {"inst": "clz Rd!=PC, Rn!=PC" , "a32": "cond|000|1011|0|1111|Rd|1111|0001|Rn"}, 43 {"inst": "cmn Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1011|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"}, 44 {"inst": "cmn Rn, Rm, {sop #n}" , "a32": "cond|000|1011|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"}, 45 {"inst": "cmn Rn, #immA" , "a32": "cond|001|1011|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W V=W"}, 46 {"inst": "cmp Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1010|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"}, 47 {"inst": "cmp Rn, Rm, {sop #n}" , "a32": "cond|000|1010|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"}, 48 {"inst": "cmp Rn, #immA" , "a32": "cond|001|1010|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W V=W"}, 49 {"inst": "cps #immZ" , "a32": "1111|000|1000|0|0010|0000|000|000|0|immZ:5"}, 50 {"inst": "cpsid #aif" , "a32": "1111|000|1000|0|1100|0000|000|aif:3|0|00000"}, 51 {"inst": "cpsid #aif, #immZ" , "a32": "1111|000|1000|0|1110|0000|000|aif:3|0|immZ:5"}, 52 {"inst": "cpsie #aif" , "a32": "1111|000|1000|0|1000|0000|000|aif:3|0|00000"}, 53 {"inst": "cpsie #aif, #immZ" , "a32": "1111|000|1000|0|1010|0000|000|aif:3|0|immZ:5"}, 54 {"inst": "eor Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0001|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 55 {"inst": "eor Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0001|0|Rn|Rd|n:5|sop:2|0|Rm"}, 56 {"inst": "eor Rd, Rn, #immA" , "a32": "cond|001|0001|0|Rn|Rd|imm:12"}, 57 {"inst": "eorS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0001|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"}, 58 {"inst": "eorS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0001|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"}, 59 {"inst": "eorS Rd!=PC, Rn, #immA" , "a32": "cond|001|0001|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"}, 60 {"inst": "eret" , "a32": "cond|000|1011|0|0000|0000|0000|0110|1110"}, 61 {"inst": "hlt #immZ" , "a32": "1110|000|1000|0|immZ:12|0111|immZ:4"}, 62 {"inst": "hvc #immZ" , "a32": "cond|000|1010|0|immZ:12|0111|immZ:4"}, 63 {"inst": "ldmda [Rn!=PC]{!}, RdList" , "a32": "cond|100|000W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 64 {"inst": "ldmdb [Rn!=PC]{!}, RdList" , "a32": "cond|100|100W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 65 {"inst": "ldmia [Rn!=PC]{!}, RdList" , "a32": "cond|100|010W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 66 {"inst": "ldmib [Rn!=PC]{!}, RdList" , "a32": "cond|100|110W|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 67 {"inst": "ldmda [Rn!=PC], RdList^" , "a32": "cond|100|0010|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 68 {"inst": "ldmdb [Rn!=PC], RdList^" , "a32": "cond|100|1010|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 69 {"inst": "ldmia [Rn!=PC], RdList^" , "a32": "cond|100|0110|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 70 {"inst": "ldmib [Rn!=PC], RdList^" , "a32": "cond|100|1110|1|Rn|immMask:16" , "imm": "GpListImm(RdList)"}, 71 {"inst": "ldr Rd, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU0W|1|Rn|Rd|n:5|sop:2|0|Rm"}, 72 {"inst": "ldr Rd, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU0W|1|Rn|Rd|off:12"}, 73 {"inst": "ldr Rd, [Rn==PC, #+/-off]" , "a32": "cond|010|1U00|1|Rn|Rd|off:12"}, 74 {"inst": "ldrb Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU1W|1|Rn|Rd|n:5|sop:2|0|Rm"}, 75 {"inst": "ldrb Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU1W|1|Rn|Rd|off:12"}, 76 {"inst": "ldrb Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|1U10|1|Rn|Rd|off:12"}, 77 {"inst": "ldrbt Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U11|1|Rn|Rd|n:5|sop:2|0|Rm"}, 78 {"inst": "ldrbt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U11|1|Rn|Rd|off:12"}, 79 {"inst": "ldrd Rd<=13, Rd2+, [Rn!=PC, +/-Rm]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rd|0000|1101|Rm"}, 80 {"inst": "ldrd Rd<=13, Rd2+, [Rn!=PC, #+/-off]{!}" , "a32": "cond|000|PU1W|0|Rn|Rd|off:4|1101|off:4"}, 81 {"inst": "ldrd Rd<=13, Rd2+, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rd|off:4|1101|off:4"}, 82 {"inst": "ldrex Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1111|1001|1111"}, 83 {"inst": "ldrexb Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1111|1001|1111"}, 84 {"inst": "ldrexd Rd<=13, Rd2+, [Rn!=PC]" , "a32": "cond|000|1101|1|Rn|Rd|1111|1001|1111"}, 85 {"inst": "ldrexh Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1111|1001|1111"}, 86 {"inst": "ldrh Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1011|Rm"}, 87 {"inst": "ldrh Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1011|off:4"}, 88 {"inst": "ldrh Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1011|off:4"}, 89 {"inst": "ldrht Rd!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1011|Rm"}, 90 {"inst": "ldrht Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1011|off:4"}, 91 {"inst": "ldrsb Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1101|Rm"}, 92 {"inst": "ldrsb Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1101|off:4"}, 93 {"inst": "ldrsb Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1101|off:4"}, 94 {"inst": "ldrsbt Rd!=PC, [Rn!=PC, +/-Rm]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1101|Rm"}, 95 {"inst": "ldrsbt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1101|off:4"}, 96 {"inst": "ldrsh Rd!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|1|Rn|Rd|0000|1111|Rm"}, 97 {"inst": "ldrsh Rd!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|1|Rn|Rd|off:4|1111|off:4"}, 98 {"inst": "ldrsh Rd!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|1|Rn|Rd|off:4|1111|off:4"}, 99 {"inst": "ldrsht Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|1|Rn|Rd|off:4|1111|off:4"}, 100 {"inst": "ldrsht Rd!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|1|Rn|Rd|0000|1111|Rm"}, 101 {"inst": "ldrt Rd!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U01|1|Rn|Rd|n:5|sop:2|0|Rm"}, 102 {"inst": "ldrt Rd!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U01|1|Rn|Rd|off:12"}, 103 {"inst": "lsl Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|000|Rn"}, 104 {"inst": "lsl Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0001|Rn"}, 105 {"inst": "lslS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|000|Rn" , "io": "N=W Z=W C=W"}, 106 {"inst": "lslS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0001|Rn" , "io": "N=W Z=W C=W"}, 107 {"inst": "lsr Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|010|Rn"}, 108 {"inst": "lsr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0011|Rn"}, 109 {"inst": "lsrS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|010|Rn" , "io": "N=W Z=W C=W"}, 110 {"inst": "lsrS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0011|Rn" , "io": "N=W Z=W C=W"}, 111 {"inst": "mcr #CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "a32": "cond|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4"}, 112 {"inst": "mcr2 #CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "a32": "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4"}, 113 {"inst": "mcrr #CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "a32": "cond|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4"}, 114 {"inst": "mcrr2 #CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "a32": "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4"}, 115 {"inst": "mla Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0001|0|Rd|Ra|Rm|1001|Rn"}, 116 {"inst": "mlaS Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0001|1|Rd|Ra|Rm|1001|Rn" , "io": "N=W Z=W"}, 117 {"inst": "mls Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|0011|0|Rd|Ra|Rm|1001|Rn"}, 118 {"inst": "mov Rd, Rn, sop Rs" , "a32": "cond|000|1101|0|0000|Rd|Rs|0|sop:2|1|Rn"}, 119 {"inst": "mov Rd, Rn, {sop #n}" , "a32": "cond|000|1101|0|0000|Rd|n:5|sop:2|0|Rn"}, 120 {"inst": "mov Rd, #immA" , "a32": "cond|001|1101|0|0000|Rd|imm:12"}, 121 {"inst": "movS Rd!=PC, Rn, sop Rs" , "a32": "cond|000|1101|1|0000|Rd|Rs|0|sop:2|1|Rn" , "io": "N=W Z=W C=W"}, 122 {"inst": "movS Rd!=PC, Rn, {sop #n}" , "a32": "cond|000|1101|1|0000|Rd|n:5|sop:2|0|Rn" , "io": "N=W Z=W C=W"}, 123 {"inst": "movS Rd!=PC, #immA" , "a32": "cond|001|1101|1|0000|Rd|imm:12" , "io": "N=W Z=W C=W"}, 124 {"inst": "movt Rx!=PC, #immZ" , "a32": "cond|001|1010|0|immZ:4|Rx|immZ:12"}, 125 {"inst": "movw Rd!=PC, #immZ" , "a32": "cond|001|1000|0|immZ:4|Rd|immZ:12"}, 126 {"inst": "mrc #CP, #op1, Rd!=PC, Cn, Cm, {#op2}" , "a32": "cond|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4"}, 127 {"inst": "mrc2 #CP, #op1, Rd!=PC, Cn, Cm, {#op2}" , "a32": "1111|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4"}, 128 {"inst": "mrrc #CP, #op1, Rd!=PC, Rd2!=Rd, Cm" , "a32": "cond|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4"}, 129 {"inst": "mrrc2 #CP, #op1, Rd!=PC, Rd2!=Rd, Cm" , "a32": "1111|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4"}, 130 {"inst": "mrs Rd!=PC, #APSR" , "a32": "cond|000|10|APSR:1|0|0|1111|Rd|0000|0000|0000"}, 131 {"inst": "msr #APSR, Rn!=PC" , "a32": "cond|000|1001|0|APSR:2|00|1111|0000|0000|Rn"}, 132 {"inst": "msr #APSR, #immA" , "a32": "cond|001|1001|0|APSR:2|00|1111|imm:12"}, 133 {"inst": "mul Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0000|0|Rd|0000|Rm|1001|Rn"}, 134 {"inst": "mulS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0000|1|Rd|0000|Rm|1001|Rn" , "io": "N=W Z=W"}, 135 {"inst": "mvn Rd!=PC, Rn!=PC, sop Rs!=PC" , "a32": "cond|000|1111|0|0000|Rd|Rs|0|sop:2|1|Rn"}, 136 {"inst": "mvn Rd, Rn, {sop #n}" , "a32": "cond|000|1111|0|0000|Rd|n:5|sop:2|0|Rn"}, 137 {"inst": "mvn Rd, #immA" , "a32": "cond|001|1111|0|0000|Rd|imm:12"}, 138 {"inst": "mvnS Rd!=PC, Rn!=PC, sop Rs!=PC" , "a32": "cond|000|1111|1|0000|Rd|Rs|0|sop:2|1|Rn" , "io": "N=W Z=W C=W"}, 139 {"inst": "mvnS Rd!=PC, Rn, {sop #n}" , "a32": "cond|000|1111|1|0000|Rd|n:5|sop:2|0|Rn" , "io": "N=W Z=W C=W"}, 140 {"inst": "mvnS Rd!=PC, #immA" , "a32": "cond|001|1111|1|0000|Rd|imm:12" , "io": "N=W Z=W C=W"}, 141 {"inst": "nop" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0000"}, 142 {"inst": "orr Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1100|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 143 {"inst": "orr Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|1100|0|Rn|Rd|n:5|sop:2|0|Rm"}, 144 {"inst": "orr Rd, Rn, #immA" , "a32": "cond|001|1100|0|Rn|Rd|imm:12"}, 145 {"inst": "orrS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1100|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"}, 146 {"inst": "orrS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|1100|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"}, 147 {"inst": "orrS Rd!=PC, Rn, #immA" , "a32": "cond|001|1100|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W"}, 148 {"inst": "pkhbt Rd!=PC, Rn!=PC, Rm!=PC, {lsl #n}" , "a32": "cond|011|0100|0|Rn|Rd|n:5|0|01|Rm"}, 149 {"inst": "pkhtb Rd!=PC, Rn!=PC, Rm!=PC, {asr #n}" , "a32": "cond|011|0100|0|Rn|Rd|n:5|1|01|Rm"}, 150 {"inst": "pld [Rn!=PC, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|1U10|1|Rn|1111|n:5|sop:2|0|Rm"}, 151 {"inst": "pld [Rn, #+/-off]" , "a32": "1111|010|1U10|1|Rn|1111|off:12"}, 152 {"inst": "pop Rd!=SP" , "a32": "cond|010|0100|1|1101|Rd|0000|0000|0100"}, 153 {"inst": "pop RdList" , "a32": "cond|100|0101|1|1101|immMask:16" , "imm": "GpListImm(RdList)"}, 154 {"inst": "push Rs!=SP" , "a32": "cond|010|1001|0|1101|Rs|0000|0000|0100"}, 155 {"inst": "push RsList" , "a32": "cond|100|1001|0|1101|immMask:16" , "imm": "GpListImm(RsList)"}, 156 {"inst": "qadd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"}, 157 {"inst": "qadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0001|Rm"}, 158 {"inst": "qadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|1001|Rm"}, 159 {"inst": "qasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0011|Rm"}, 160 {"inst": "qdadd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"}, 161 {"inst": "qdsub Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"}, 162 {"inst": "qsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0101|Rm"}, 163 {"inst": "qsub Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rm|Rd|0000|0101|Rn" , "io": "Q=X"}, 164 {"inst": "qsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|0111|Rm"}, 165 {"inst": "qsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|0|Rn|Rd|1111|1111|Rm"}, 166 {"inst": "rbit Rd!=PC, Rn!=PC" , "a32": "cond|011|0111|1|1111|Rd|1111|0011|Rn"}, 167 {"inst": "rev Rd!=PC, Rn!=PC" , "a32": "cond|011|0101|1|1111|Rd|1111|0011|Rn"}, 168 {"inst": "rev16 Rd!=PC, Rn!=PC" , "a32": "cond|011|0101|1|1111|Rd|1111|1011|Rn"}, 169 {"inst": "revsh Rd!=PC, Rn!=PC" , "a32": "cond|011|0111|1|1111|Rd|1111|1011|Rn"}, 170 {"inst": "rfeda [Rn!=PC]{!}" , "a32": "1111|100|000|W|1|Rn|0000|1010|0000|0000"}, 171 {"inst": "rfedb [Rn!=PC]{!}" , "a32": "1111|100|100|W|1|Rn|0000|1010|0000|0000"}, 172 {"inst": "rfeia [Rn!=PC]{!}" , "a32": "1111|100|010|W|1|Rn|0000|1010|0000|0000"}, 173 {"inst": "rfeib [Rn!=PC]{!}" , "a32": "1111|100|110|W|1|Rn|0000|1010|0000|0000"}, 174 {"inst": "ror Rd, Rn, #n" , "a32": "cond|000|1101|0|0000|Rd|n:5|110|Rn"}, 175 {"inst": "ror Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|0|0000|Rd|Rm|0111|Rn"}, 176 {"inst": "rorS Rd, Rn, #n" , "a32": "cond|000|1101|1|0000|Rd|n:5|110|Rn" , "io": "N=W Z=W C=W"}, 177 {"inst": "rorS Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1101|1|0000|Rd|Rm|0111|Rn" , "io": "N=W Z=W C=W"}, 178 {"inst": "rsb Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0011|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 179 {"inst": "rsb Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0011|0|Rn|Rd|n:5|sop:2|0|Rm"}, 180 {"inst": "rsb Rd, Rn, #immA" , "a32": "cond|001|0011|0|Rn|Rd|imm:12"}, 181 {"inst": "rsbS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0011|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"}, 182 {"inst": "rsbS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0011|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"}, 183 {"inst": "rsbS Rd!=PC, Rn, #immA" , "a32": "cond|001|0011|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"}, 184 {"inst": "rsc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0111|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 185 {"inst": "rsc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0111|0|Rn|Rd|n:5|sop:2|0|Rm"}, 186 {"inst": "rsc Rd, Rn, #immA" , "a32": "cond|001|0111|0|Rn|Rd|imm:12"}, 187 {"inst": "rscS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0111|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"}, 188 {"inst": "rscS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0111|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"}, 189 {"inst": "rscS Rd!=PC, Rn, #immA" , "a32": "cond|001|0111|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"}, 190 {"inst": "rrx Rd, Rn" , "a32": "cond|000|1101|0|0000|Rd|00000|110|Rn" , "io": "C=R"}, 191 {"inst": "rrxS Rd, Rn" , "a32": "cond|000|1101|1|0000|Rd|00000|110|Rn" , "io": "N=W Z=W C=X"}, 192 {"inst": "sadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0001|Rm" , "io": "GE=W"}, 193 {"inst": "sadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|1001|Rm" , "io": "GE=W"}, 194 {"inst": "sasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0011|Rm" , "io": "GE=W"}, 195 {"inst": "sbc Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0110|0|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "C=R"}, 196 {"inst": "sbc Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0110|0|Rn|Rd|n:5|sop:2|0|Rm" , "io": "C=R"}, 197 {"inst": "sbc Rd, Rn, #immA" , "a32": "cond|001|0110|0|Rn|Rd|imm:12" , "io": "C=R"}, 198 {"inst": "sbcS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0110|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=X V=W"}, 199 {"inst": "sbcS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0110|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=X V=W"}, 200 {"inst": "sbcS Rd!=PC, Rn, #immA" , "a32": "cond|001|0110|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=X V=W"}, 201 {"inst": "sbfx Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1101|widthM1:5|Rd|lsb:5|101|Rn" , "imm": "SbfxUbfxImm(lsb, width)"}, 202 {"inst": "sel Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0100|0|Rn|Rd|1111|1011|Rm" , "io": "GE=R"}, 203 {"inst": "setend #immZ" , "a32": "1111|000|1000|0|0001|0000|00|immZ:1|0|0000|0000" , "ext": "ARMv8-"}, 204 {"inst": "shadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0001|Rm"}, 205 {"inst": "shadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|1001|Rm"}, 206 {"inst": "shasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0011|Rm"}, 207 {"inst": "shsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0101|Rm"}, 208 {"inst": "shsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|0111|Rm"}, 209 {"inst": "shsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0001|1|Rn|Rd|1111|1111|Rm"}, 210 {"inst": "smlabb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1000|Rn" , "io": "Q=X"}, 211 {"inst": "smlabt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1100|Rn" , "io": "Q=X"}, 212 {"inst": "smlatb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1010|Rn" , "io": "Q=X"}, 213 {"inst": "smlatt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1000|0|Rd|Ra|Rm|1110|Rn" , "io": "Q=X"}, 214 {"inst": "smlad Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0001|Rn" , "io": "Q=X"}, 215 {"inst": "smladx Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0011|Rn" , "io": "Q=X"}, 216 {"inst": "smlal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0111|0|RxHi|RxLo|Rm|1001|Rn"}, 217 {"inst": "smlalS RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0111|1|RxHi|RxLo|Rm|1001|Rn" , "io": "N=W Z=W"}, 218 {"inst": "smlalbb RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1000|Rn"}, 219 {"inst": "smlalbt RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1100|Rn"}, 220 {"inst": "smlaltb RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1010|Rn"}, 221 {"inst": "smlaltt RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|RxHi|RxLo|Rm|1110|Rn"}, 222 {"inst": "smlald RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0001|Rn"}, 223 {"inst": "smlaldx RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0011|Rn"}, 224 {"inst": "smlawb Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1001|0|Rd|Ra|Rm|1000|Rn" , "io": "Q=X"}, 225 {"inst": "smlawt Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|000|1001|0|Rd|Ra|Rm|1100|Rn" , "io": "Q=X"}, 226 {"inst": "smlsd Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0101|Rn" , "io": "Q=X"}, 227 {"inst": "smlsdx Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1000|0|Rd|Ra|Rm|0111|Rn" , "io": "Q=X"}, 228 {"inst": "smlsld RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0101|Rn"}, 229 {"inst": "smlsldx RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|0|RxHi|RxLo|Rm|0111|Rn"}, 230 {"inst": "smmla Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|0001|Rn"}, 231 {"inst": "smmlar Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|0011|Rn"}, 232 {"inst": "smmls Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|1101|Rn"}, 233 {"inst": "smmlsr Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1010|1|Rd|Ra|Rm|1111|Rn"}, 234 {"inst": "smmul Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|1|Rd|1111|Rm|0001|Rn"}, 235 {"inst": "smmulr Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1010|1|Rd|1111|Rm|0011|Rn"}, 236 {"inst": "smuad Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0001|Rn" , "io": "Q=X"}, 237 {"inst": "smuadx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0011|Rn" , "io": "Q=X"}, 238 {"inst": "smulbb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1000|Rn"}, 239 {"inst": "smulbt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1100|Rn"}, 240 {"inst": "smultb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1010|Rn"}, 241 {"inst": "smultt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1011|0|Rd|0000|Rm|1110|Rn"}, 242 {"inst": "smull RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0110|0|RdHi|RdLo|Rm|1001|Rn"}, 243 {"inst": "smullS RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0110|1|RdHi|RdLo|Rm|1001|Rn" , "io": "N=W Z=W"}, 244 {"inst": "smulwb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rd|0000|Rm|1010|Rn"}, 245 {"inst": "smulwt Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rd|0000|Rm|1110|Rn"}, 246 {"inst": "smusd Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0101|Rn"}, 247 {"inst": "smusdx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|0|Rd|1111|Rm|0111|Rn"}, 248 {"inst": "srsda [Rn==SP]{!}, #mode" , "a32": "1111|100|001|W|0|1101|0000|0101|000|mode:5"}, 249 {"inst": "srsdb [Rn==SP]{!}, #mode" , "a32": "1111|100|101|W|0|1101|0000|0101|000|mode:5"}, 250 {"inst": "srsia [Rn==SP]{!}, #mode" , "a32": "1111|100|011|W|0|1101|0000|0101|000|mode:5"}, 251 {"inst": "srsib [Rn==SP]{!}, #mode" , "a32": "1111|100|111|W|0|1101|0000|0101|000|mode:5"}, 252 {"inst": "ssat Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0101|imm:5|Rd|00000|00|1|Rn" , "imm": "SsatImm(sat)", "io": "Q=X"}, 253 {"inst": "ssat Rd!=PC, #sat, Rn!=PC, lsl_or_asr #n" , "a32": "cond|011|0101|imm:5|Rd|n:5|sop:2|1|Rn" , "imm": "SsatImm(sat, n)", "io": "Q=X"}, 254 {"inst": "ssat16 Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0101|0|imm:4|Rd|1111|0011|Rn" , "imm": "Ssat16Imm(sat)", "io": "Q=X"}, 255 {"inst": "ssax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0101|Rm" , "io": "GE=W"}, 256 {"inst": "ssub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|0111|Rm" , "io": "GE=W"}, 257 {"inst": "ssub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0000|1|Rn|Rd|1111|1111|Rm" , "io": "GE=W"}, 258 {"inst": "stmda [Rn!=PC]{!}, RsList" , "a32": "cond|100|000W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 259 {"inst": "stmdb [Rn!=PC]{!}, RsList" , "a32": "cond|100|100W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 260 {"inst": "stmia [Rn!=PC]{!}, RsList" , "a32": "cond|100|010W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 261 {"inst": "stmib [Rn!=PC]{!}, RsList" , "a32": "cond|100|110W|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 262 {"inst": "stmda [Rn!=PC], RsList^" , "a32": "cond|100|0010|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 263 {"inst": "stmdb [Rn!=PC], RsList^" , "a32": "cond|100|1010|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 264 {"inst": "stmia [Rn!=PC], RsList^" , "a32": "cond|100|0110|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 265 {"inst": "stmib [Rn!=PC], RsList^" , "a32": "cond|100|1110|0|Rn|immMask:16" , "imm": "GpListImm(RsList)"}, 266 {"inst": "str Rs, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU0W|0|Rn|Rs|n:5|sop:2|0|Rm"}, 267 {"inst": "str Rs, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU0W|0|Rn|Rs|off:12"}, 268 {"inst": "str Rs, [Rn==PC, #+/-off]" , "a32": "cond|010|1U00|0|Rn|Rs|off:12"}, 269 {"inst": "strb Rs!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]{@}{!}" , "a32": "cond|011|PU1W|0|Rn|Rs|n:5|sop:2|0|Rm"}, 270 {"inst": "strb Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|010|PU1W|0|Rn|Rs|off:12"}, 271 {"inst": "strb Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|1U10|0|Rn|Rs|off:12"}, 272 {"inst": "strbt Rs!=PC, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U11|0|Rn|Rs|n:5|sop:2|0|Rm"}, 273 {"inst": "strbt Rs!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U11|0|Rn|Rs|off:12"}, 274 {"inst": "strbt Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|010|0U11|0|Rn|Rs|off:12"}, 275 {"inst": "strd Rs<=13, Rs2+, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rs|0000|1111|Rm"}, 276 {"inst": "strd Rs<=13, Rs2+, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|0|Rn|Rs|off:4|1111|off:4"}, 277 {"inst": "strd Rs<=13, Rs2+, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rs|off:4|1111|off:4"}, 278 {"inst": "strex Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|Rd|1111|1001|Rs"}, 279 {"inst": "strexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|Rd|1111|1001|Rs"}, 280 {"inst": "strexd Rd!=PC, Rs!=PC, Rs2+, [Rn!=PC]" , "a32": "cond|000|1101|0|Rn|Rd|1111|1001|Rs"}, 281 {"inst": "strexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|Rd|1111|1001|Rs"}, 282 {"inst": "strh Rs!=PC, [Rn!=PC, +/-Rm!=PC]{@}{!}" , "a32": "cond|000|PU0W|0|Rn|Rs|0000|1011|Rm"}, 283 {"inst": "strh Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "a32": "cond|000|PU1W|0|Rn|Rs|off:4|1011|off:4"}, 284 {"inst": "strh Rs!=PC, [Rn==PC, #+/-off]" , "a32": "cond|000|1U10|0|Rn|Rs|off:4|1011|off:4"}, 285 {"inst": "strht Rs!=PC, [Rn!=PC, +/-Rm!=PC]@" , "a32": "cond|000|0U01|0|Rn|Rs|0000|1011|Rm"}, 286 {"inst": "strht Rs!=PC, [Rn!=PC, #+/-off]@" , "a32": "cond|000|0U11|0|Rn|Rs|off:4|1011|off:4"}, 287 {"inst": "strt Rs, [Rn!=PC, +/-Rm!=PC, {sop #n}]@" , "a32": "cond|011|0U01|0|Rn|Rs|n:5|sop:2|0|Rm"}, 288 {"inst": "strt Rs, [Rn!=PC, #+/-off]@" , "a32": "cond|010|0U01|0|Rn|Rs|off:12"}, 289 {"inst": "sub Rd, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0010|0|Rn|Rd|Rs|0|sop:2|1|Rm"}, 290 {"inst": "sub Rd, Rn, Rm, {sop #n}" , "a32": "cond|000|0010|0|Rn|Rd|n:5|sop:2|0|Rm"}, 291 {"inst": "sub Rd, Rn, #immA" , "a32": "cond|001|0010|0|Rn|Rd|imm:12"}, 292 {"inst": "subS Rd!=PC, Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|0010|1|Rn|Rd|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W V=W"}, 293 {"inst": "subS Rd!=PC, Rn, Rm, {sop #n}" , "a32": "cond|000|0010|1|Rn|Rd|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W V=W"}, 294 {"inst": "subS Rd!=PC, Rn, #immA" , "a32": "cond|001|0010|1|Rn|Rd|imm:12" , "io": "N=W Z=W C=W V=W"}, 295 {"inst": "svc #immZ" , "a32": "cond|1111|immZ:24"}, 296 {"inst": "sxtab Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0101|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"}, 297 {"inst": "sxtab16 Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0100|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"}, 298 {"inst": "sxtah Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0101|1|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"}, 299 {"inst": "sxtb Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0101|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"}, 300 {"inst": "sxtb16 Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0100|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"}, 301 {"inst": "sxth Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0101|1|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"}, 302 {"inst": "teq Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1001|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"}, 303 {"inst": "teq Rn, Rm, {sop #n}" , "a32": "cond|000|1001|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"}, 304 {"inst": "teq Rn, #immA" , "a32": "cond|001|1001|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W"}, 305 {"inst": "tst Rn!=PC, Rm!=PC, sop Rs!=PC" , "a32": "cond|000|1000|1|Rn|0000|Rs|0|sop:2|1|Rm" , "io": "N=W Z=W C=W"}, 306 {"inst": "tst Rn, Rm, {sop #n}" , "a32": "cond|000|1000|1|Rn|0000|n:5|sop:2|0|Rm" , "io": "N=W Z=W C=W"}, 307 {"inst": "tst Rn, #immA" , "a32": "cond|001|1000|1|Rn|0000|imm:12" , "io": "N=W Z=W C=W"}, 308 {"inst": "uadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0001|Rm" , "io": "GE=W"}, 309 {"inst": "uadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|1001|Rm" , "io": "GE=W"}, 310 {"inst": "uasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0011|Rm" , "io": "GE=W"}, 311 {"inst": "ubfx Rd!=PC, Rn!=PC, #lsb, #width" , "a32": "cond|011|1111|widthM1:5|Rd|lsb:5|101|Rn" , "imm": "SbfxUbfxImm(lsb, width)"}, 312 {"inst": "udf #immZ" , "a32": "1110|011|1111|1|immZ:12|1111|immZ:4"}, 313 {"inst": "uhadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|1001|Rm"}, 314 {"inst": "uhadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0001|Rm"}, 315 {"inst": "uhasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0011|Rm"}, 316 {"inst": "uhsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0101|Rm"}, 317 {"inst": "uhsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|0111|Rm"}, 318 {"inst": "uhsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|1|Rn|Rd|1111|1111|Rm"}, 319 {"inst": "umaal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0010|0|RxHi|RxLo|Rm|1001|Rn"}, 320 {"inst": "umlal RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0101|0|RxHi|RxLo|Rm|1001|Rn"}, 321 {"inst": "umlalS RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0101|1|RxHi|RxLo|Rm|1001|Rn" , "io": "N=W Z=W"}, 322 {"inst": "umull RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0100|0|RdHi|RdLo|Rm|1001|Rn"}, 323 {"inst": "umullS RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|0100|1|RdHi|RdLo|Rm|1001|Rn" , "io": "N=W Z=W"}, 324 {"inst": "uqadd16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0001|Rm"}, 325 {"inst": "uqadd8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|1001|Rm"}, 326 {"inst": "uqasx Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0011|Rm"}, 327 {"inst": "uqsax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0101|Rm"}, 328 {"inst": "uqsub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|0111|Rm"}, 329 {"inst": "uqsub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0011|0|Rn|Rd|1111|1111|Rm"}, 330 {"inst": "usad8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1100|0|Rd|1111|Rm|0001|Rn"}, 331 {"inst": "usada8 Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "a32": "cond|011|1100|0|Rd|Ra|Rm|0001|Rn"}, 332 {"inst": "usat Rd!=PC, #sat, Rn!=PC, {lsl_or_asr #n}" , "a32": "cond|011|0111|sat:5|Rd|n:5|sop:2|1|Rn"}, 333 {"inst": "usat16 Rd!=PC, #sat, Rn!=PC" , "a32": "cond|011|0111|0|sat:4|Rd|1111|0011|Rn"}, 334 {"inst": "usax Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0101|Rm" , "io": "GE=W"}, 335 {"inst": "usub16 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|0111|Rm" , "io": "GE=W"}, 336 {"inst": "usub8 Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|0010|1|Rn|Rd|1111|1111|Rm" , "io": "GE=W"}, 337 {"inst": "uxtab Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0111|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"}, 338 {"inst": "uxtab16 Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0110|0|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"}, 339 {"inst": "uxtah Rd!=PC, Rn!=PC, Rm!=PC, {ror #n}" , "a32": "cond|011|0111|1|Rn|Rd|imm:2|00|0111|Rm" , "imm": "Ror8Imm(n)"}, 340 {"inst": "uxtb Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0111|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"}, 341 {"inst": "uxtb16 Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0110|0|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"}, 342 {"inst": "uxth Rd!=PC, Rn!=PC, {ror #n}" , "a32": "cond|011|0111|1|1111|Rd|imm:2|00|0111|Rn" , "imm": "Ror8Imm(n)"}, 343 {"inst": "wfe" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0010"}, 344 {"inst": "wfi" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0011"}, 345 {"inst": "yield" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0001"} 346 ]}, 347 348 {"category": "GP", "data": [ 349 {"inst": "adc Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|101|Rm:3|Rx:3" , "it": "in" , "io": "C=R"}, 350 {"inst": "adc Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1010|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "C=R"}, 351 {"inst": "adc Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "C=R"}, 352 {"inst": "adcS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|101|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"}, 353 {"inst": "adcS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1010|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"}, 354 {"inst": "adcS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=X V=W", "mod": "APSR_IF_NOT_PC"}, 355 {"inst": "add Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|100|Rm:3|Rn:3|Rd:3" , "it": "in"}, 356 {"inst": "add Rx!=XX, Rx!=XX, Rm!=XX" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "in"}, 357 {"inst": "add Rx, Rx, Rm==SP" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "any"}, 358 {"inst": "add Rx==SP, Rx==SP, Rm" , "t16": "0100|010|0|Rx:1|Rm:4|Rx:3" , "it": "any"}, 359 {"inst": "add Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|0|Rx:3|immZ:8" , "it": "in"}, 360 {"inst": "add Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|110|immZ:3|Rn:3|Rd:3" , "it": "in"}, 361 {"inst": "add Rx==SP, Rx==SP, #immZ*4" , "t16": "1011|00000|immZ:7" , "it": "any"}, 362 {"inst": "add Rd!=SP, Rn==SP, #immZ*4" , "t16": "1010|1|Rd:3|immZ:8" , "it": "any"}, 363 {"inst": "add Rd!=XX, Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 364 {"inst": "add Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "mod": "LSL_3_IF_SP"}, 365 {"inst": "add Rd!=XX, Rn!=PC, #immZ" , "t32": "1111|0|immZ:1|1|0000|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"}, 366 {"inst": "add Rd!=XX, Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 367 {"inst": "add Rd!=PC, Rn==SP, #immZ" , "t32": "1111|0|immZ:1|1|0000|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"}, 368 {"inst": "add Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1000|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 369 {"inst": "addS Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|0|Rx:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W V=W"}, 370 {"inst": "addS Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|110|immZ:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"}, 371 {"inst": "addS Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|100|Rm:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"}, 372 {"inst": "addS Rd!=XX, Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"}, 373 {"inst": "addS Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W", "mod": "LSL_3_IF_SP"}, 374 {"inst": "addS Rd!=XX, Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 375 {"inst": "addS Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 376 {"inst": "adr Rd!=HI, #relZ*4" , "t16": "1010|0|Rd:3|relZ:8" , "it": "any"}, 377 {"inst": "adr Rd!=XX, #relZ" , "t32": "1111|0|relZ:1|10N0N|0|1111|0|relZ:3|Rd|relZ:8" , "it": "any"}, 378 {"inst": "and Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|000|Rm:3|Rx:3" , "it": "in"}, 379 {"inst": "and Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0000|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 380 {"inst": "and Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 381 {"inst": "andS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|000|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 382 {"inst": "andS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0000|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 383 {"inst": "andS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W", "mod": "APSR_IF_NOT_PC"}, 384 {"inst": "asr Rd!=HI, Rn!=HI, #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "in"}, 385 {"inst": "asr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "in"}, 386 {"inst": "asr Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|10|Rn" , "it": "any"}, 387 {"inst": "asr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0010|0|Rn|1111|Rd|0000|Rm" , "it": "any"}, 388 {"inst": "asrS Rd!=HI, Rn!=HI, #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 389 {"inst": "asrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 390 {"inst": "asrS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|10|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 391 {"inst": "asrS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0010|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 392 {"inst": "b #relS*2" , "t16": "1110|0|relS:11" , "it": "out last"}, 393 {"inst": "b #relS*2" , "t32": "1111|0|relS[23]|relS[20:11]|10|ja|1|jb|relS[10:0]" , "it": "out last", "calc": {"ja": "relS[23] ^ relS[22] ^ 1", "jb": "relS[23] ^ relS[21] ^ 1"}}, 394 {"inst": "b #relS*2" , "t16": "1101|cond|relS:8" , "it": "out"}, 395 {"inst": "b #relS*2" , "t32": "1111|0|relS[19]|cond|relS[16:11]|10|ja|0|jb|relS[10:0]" , "it": "out" , "calc": {"ja": "relS[19] ^ relS[18] ^ 1", "jb": "relS[19] ^ relS[17] ^ 1"}}, 396 {"inst": "bfc Rd!=XX, #lsb, #width" , "t32": "1111|001|1011|0|1111|0|lsb:3|Rd|lsb:2|0|msb:5" , "it": "any", "imm": "BfcBfiImm(lsb, width)"}, 397 {"inst": "bfi Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1011|0|Rn|0|lsb:3|Rd|lsb:2|0|msb:5" , "it": "any", "imm": "BfcBfiImm(lsb, width)"}, 398 {"inst": "bic Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|110|Rm:3|Rx:3" , "it": "in"}, 399 {"inst": "bic Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0001|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 400 {"inst": "bic Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0001|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 401 {"inst": "bicS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|110|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 402 {"inst": "bicS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0001|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 403 {"inst": "bicS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0001|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 404 {"inst": "bkpt #immZ" , "t16": "1011|111|0|immZ:8" , "it": "uncond"}, 405 {"inst": "bl #relS*2" , "t32": "1111|0|relS[23]|relS[20:11]|11|ja|1|jb|relS[10:0]" , "it": "out last", "calc": {"ja": "relS[23] ^ relS[22] ^ 1", "jb": "relS[23] ^ relS[21] ^ 1"}}, 406 {"inst": "blx Rm!=PC" , "t16": "0100|011|11|Rm:4|000" , "it": "out last"}, 407 {"inst": "blx #relS*4" , "t32": "1111|0|relS[22]|relS[19:10]|11|ja|0|jb|relS[9:0]|0" , "it": "out last", "calc": {"ja": "relS[22] ^ relS[21] ^ 1", "jb": "relS[22] ^ relS[20] ^ 1"}}, 408 {"inst": "bx Rm" , "t16": "0100|011|10|Rm:4|000" , "it": "out last"}, 409 {"inst": "bxj Rm!=XX" , "t32": "1111|001|1110|0|Rm|1000|1111|00000000" , "it": "out last"}, 410 {"inst": "cbz Rn!=HI, #relZ*2" , "t16": "1011|00|relZ:1|1|relZ:5|Rn:3" , "it": "out"}, 411 {"inst": "cbnz Rn!=HI, #relZ*2" , "t16": "1011|10|relZ:1|1|relZ:5|Rn:3" , "it": "out"}, 412 {"inst": "clz Rd!=XX, Rn!=XX" , "t32": "1111|101|0101|1|Rm|1111|Rd|1000|Rn" , "it": "any"}, 413 {"inst": "cmn Rn!=HI, Rm!=HI" , "t16": "0100|001|011|Rm:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W"}, 414 {"inst": "cmn Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1000|1|Rn|0|n:3|1111|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"}, 415 {"inst": "cmn Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1000|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 416 {"inst": "cmp Rn!=HI, #immZ" , "t16": "0010|1|Rn:3|immZ:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 417 {"inst": "cmp Rn!=HI, Rm!=HI" , "t16": "0100|001|010|Rm:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W"}, 418 {"inst": "cmp Rn!=PC, Rm!=PC" , "t16": "0100|010|1|Rn:1|Rm:4|Rn:3" , "it": "any", "io": "N=W Z=W C=W V=W", "mod": "UNPRED_IF_ALL_LOW"}, 419 {"inst": "cmp Rn!=PC, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|1111|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"}, 420 {"inst": "cmp Rn!=PC, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 421 {"inst": "dbg #immZ" , "t32": "1111|001|1101|0|1111|1000|0000|1111|immZ:4" , "it": "any"}, 422 {"inst": "eor Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|001|Rm:3|Rx:3" , "it": "in"}, 423 {"inst": "eor Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0100|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 424 {"inst": "eor Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 425 {"inst": "eorS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|001|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 426 {"inst": "eorS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0100|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 427 {"inst": "eorS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 428 {"inst": "hlt #immZ" , "t16": "1011|1010|10|immZ:6" , "it": "out", "ext": "ARMv8+"}, 429 {"inst": "it #cond!=15" , "t16": "1011|111|1|cond[3:0]|1000" , "it": "out def"}, 430 {"inst": "ite #cond!=15" , "t16": "1011|111|1|cond[3:0]|X100" , "it": "out def"}, 431 {"inst": "itee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"}, 432 {"inst": "iteee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 433 {"inst": "iteet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 434 {"inst": "itet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"}, 435 {"inst": "itete #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 436 {"inst": "itett #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 437 {"inst": "itt #cond!=15" , "t16": "1011|111|1|cond[3:0]|X100" , "it": "out def"}, 438 {"inst": "itte #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"}, 439 {"inst": "ittee #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 440 {"inst": "ittet #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 441 {"inst": "ittt #cond!=15" , "t16": "1011|111|1|cond[3:0]|XY10" , "it": "out def"}, 442 {"inst": "ittte #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 443 {"inst": "itttt #cond!=15" , "t16": "1011|111|1|cond[3:0]|XYZ1" , "it": "out def"}, 444 {"inst": "ldmia [Rn!=HI]{!}, RdList" , "t16": "1100|1|Rn:3|imm:8" , "it": "any", "imm": "GpListImm(RdList, 0xFF)"}, 445 {"inst": "ldmia [Rn!=PC]{!}, RdList" , "t32": "1110|100|010W|1|Rn|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RdList, 0xDFFF)"}, 446 {"inst": "ldmdb [Rn!=PC]{!}, RdList" , "t32": "1110|100|100W|1|Rn|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RdList, 0xDFFF)"}, 447 {"inst": "ldr Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|100|Rm:3|Rn:3|Rd:3" , "it": "any"}, 448 {"inst": "ldr Rd, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0010|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"}, 449 {"inst": "ldr Rd!=HI, [Rn!=HI, #off*4]" , "t16": "0110|1|off:5|Rn:3|Rd:3" , "it": "any"}, 450 {"inst": "ldr Rd!=HI, [Rn==SP, #off*4]" , "t16": "1001|1|Rd:3|off:8" , "it": "any"}, 451 {"inst": "ldr Rd!=HI, [Rn==PC, #off*4]" , "t16": "0100|1|Rd:3|off:8" , "it": "any"}, 452 {"inst": "ldr Rd, [Rn!=PC, #off]" , "t32": "1111|100|0110|1|Rn|Rd|off:12" , "it": "any"}, 453 {"inst": "ldr Rd, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0010|1|Rn|Rd|1PUW|off:8" , "it": "any"}, 454 {"inst": "ldr Rd, [Rn==PC, #+/-off]" , "t32": "1111|100|0U10|1|Rn|Rd|off:12" , "it": "any"}, 455 {"inst": "ldrb Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|110|Rm:3|Rn:3|Rd:3" , "it": "any"}, 456 {"inst": "ldrb Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"}, 457 {"inst": "ldrb Rd!=HI, [Rn!=HI, #off*4]" , "t16": "0111|1|off:5|Rn:3|Rd:3" , "it": "any"}, 458 {"inst": "ldrb Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0100|1|Rn|Rd|off:12" , "it": "any"}, 459 {"inst": "ldrb Rd!=XX, [Rn!=PC, #+/-off]{!}" , "t32": "1111|100|0000|1|Rn|Rd|1PUW|off:8" , "it": "any"}, 460 {"inst": "ldrb Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|0U00|1|Rn|Rd|off:12" , "it": "any"}, 461 {"inst": "ldrbt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0000|1|Rn|Rd|1110|off:8" , "it": "any"}, 462 {"inst": "ldrd Rd!=XX, Rd2!=XX, [Rn==PC, #+/-off*4]" , "t32": "1110|100|1U10|1|Rn|Rd|Rd2|off:8" , "it": "any"}, 463 {"inst": "ldrd Rd!=XX, Rd2!=XX, [Rn!=PC, #+/-off*4]{@}{!}" , "t32": "1110|100|PU1W|1|Rn|Rd|Rd2|off:8" , "it": "any"}, 464 {"inst": "ldrex Rd!=XX, [Rn!=PC, #off*4]" , "t32": "1110|100|0010|1|Rn|Rd|1111|off:8" , "it": "any"}, 465 {"inst": "ldrh Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|101|Rm:3|Rn:3|Rd:3" , "it": "any"}, 466 {"inst": "ldrh Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"}, 467 {"inst": "ldrh Rd!=HI, [Rn!=HI, #off*4]" , "t16": "1000|1|off:5|Rn:3|Rd:3" , "it": "any"}, 468 {"inst": "ldrh Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0101|1|Rn|Rd|off:12" , "it": "any"}, 469 {"inst": "ldrh Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0001|1|Rn|Rd|1PUW|off:8" , "it": "any"}, 470 {"inst": "ldrh Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|0U01|1|Rn|Rd|off:12" , "it": "any"}, 471 {"inst": "ldrht Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0001|1|Rn|Rd|1110|off:8" , "it": "any"}, 472 {"inst": "ldrsb Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|011|Rm:3|Rn:3|Rd:3" , "it": "any"}, 473 {"inst": "ldrsb Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1000|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"}, 474 {"inst": "ldrsb Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1100|1|Rn|Rd|off:12" , "it": "any"}, 475 {"inst": "ldrsb Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|1000|1|Rn|Rd|1PUW|off:8" , "it": "any"}, 476 {"inst": "ldrsb Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|1U00|1|Rn|Rd|off:12" , "it": "any"}, 477 {"inst": "ldrsbt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1000|1|Rn|Rd|1110|off:8" , "it": "any"}, 478 {"inst": "ldrsh Rd!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|111|Rm:3|Rn:3|Rd:3" , "it": "any"}, 479 {"inst": "ldrsh Rd!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1001|1|Rn|Rd|0|00000|n:2|Rm" , "it": "any"}, 480 {"inst": "ldrsh Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1101|1|Rn|Rd|off:12" , "it": "any"}, 481 {"inst": "ldrsh Rd!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|1001|1|Rn|Rd|1PUW|off:8" , "it": "any"}, 482 {"inst": "ldrsh Rd!=XX, [Rn==PC, #+/-off]" , "t32": "1111|100|1U01|1|Rn|Rd|off:12" , "it": "any"}, 483 {"inst": "ldrsht Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|1001|1|Rn|Rd|1110|off:8" , "it": "any"}, 484 {"inst": "ldrt Rd!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0010|1|Rn|Rd|1110|off:8" , "it": "any"}, 485 {"inst": "lsl Rd!=HI, Rn!=HI, #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "in"}, 486 {"inst": "lsl Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|00|Rn" , "it": "any"}, 487 {"inst": "lsl Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "in"}, 488 {"inst": "lsl Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0000|0|Rn|1111|Rd|0000|Rm" , "it": "any"}, 489 {"inst": "lslS Rd!=HI, Rn!=HI, #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 490 {"inst": "lslS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|00|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 491 {"inst": "lslS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 492 {"inst": "lslS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1110|101|0000|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 493 {"inst": "lsr Rd!=HI, Rn!=HI, #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "in"}, 494 {"inst": "lsr Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|01|Rn" , "it": "any"}, 495 {"inst": "lsr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "in"}, 496 {"inst": "lsr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0001|0|Rn|1111|Rd|0000|Rm" , "it": "any"}, 497 {"inst": "lsrS Rd!=HI, Rn!=HI, #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 498 {"inst": "lsrS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|01|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 499 {"inst": "lsrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 500 {"inst": "lsrS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1110|101|0001|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 501 {"inst": "mcr #CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "t32": "1110|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ext": "ARMv6T2+"}, 502 {"inst": "mcr2 #CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "t32": "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ext": "ARMv6T2+"}, 503 {"inst": "mcrr #CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "t32": "1110|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ext": "ARMv6T2+"}, 504 {"inst": "mcrr2 #CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "t32": "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ext": "ARMv6T2+"}, 505 {"inst": "mla Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1000|0|Rn|Ra|Rd|0000|Rm" , "it": "any"}, 506 {"inst": "mls Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1000|0|Rn|Ra|Rd|0001|Rm" , "it": "any"}, 507 {"inst": "mov Rd, Rn" , "t16": "0100|0110|Rd:1|Rn:4|Rd:3" , "it": "in", "mod": "ARMv6T2_IF_LOW"}, 508 {"inst": "mov Rx!=HI, Rx!=HI, lsl Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "in"}, 509 {"inst": "mov Rx!=HI, Rx!=HI, lsr Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "in"}, 510 {"inst": "mov Rx!=HI, Rx!=HI, asr Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "in"}, 511 {"inst": "mov Rx!=HI, Rx!=HI, ror Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "in"}, 512 {"inst": "mov Rd!=HI, Rn!=HI, lsl #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "in"}, 513 {"inst": "mov Rd!=HI, Rn!=HI, lsr #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "in"}, 514 {"inst": "mov Rd!=HI, Rn!=HI, asr #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "in"}, 515 {"inst": "mov Rd!=HI, #immZ" , "t16": "0010|0|Rd:3|immZ:8" , "it": "in"}, 516 {"inst": "mov Rd!=PC, Rn" , "t32": "1110|101|0010|0|1111|0000|Rd|0000|Rn" , "it": "any", "mod": "UNPRED_COMPLEX"}, 517 {"inst": "mov Rd!=XX, Rn!=XX, sop #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any"}, 518 {"inst": "mov Rd!=XX, Rn!=XX, sop Rm!=XX" , "t32": "1111|101|00|sop:2|0|Rn|1111|Rd|0000|Rm" , "it": "any"}, 519 {"inst": "mov Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|0|1111|0|imm:3|Rd|imm:8" , "it": "any"}, 520 {"inst": "movS Rd!=HI, Rn!=HI" , "t16": "0000|0000|00|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 521 {"inst": "movS Rx!=HI, Rx!=HI, lsl Rm!=HI" , "t16": "0100|000|010|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 522 {"inst": "movS Rx!=HI, Rx!=HI, lsr Rm!=HI" , "t16": "0100|000|011|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 523 {"inst": "movS Rx!=HI, Rx!=HI, asr Rm!=HI" , "t16": "0100|000|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 524 {"inst": "movS Rx!=HI, Rx!=HI, ror Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 525 {"inst": "movS Rd!=HI, Rn!=HI, lsl #n" , "t16": "0000|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 526 {"inst": "movS Rd!=HI, Rn!=HI, lsr #n" , "t16": "0000|1|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 527 {"inst": "movS Rd!=HI, Rn!=HI, asr #n" , "t16": "0001|0|n:5|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 528 {"inst": "movS Rd!=HI, #immZ" , "t16": "0010|0|Rd:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W"}, 529 {"inst": "movS Rd!=XX, Rn" , "t32": "1110|101|0010|1|1111|0000|Rd|0000|Rn" , "it": "any", "io": "N=W Z=W C=W", "mod": "UNPRED_COMPLEX"}, 530 {"inst": "movS Rd!=XX, Rn!=XX, sop Rm!=XX" , "t32": "1110|101|00|sop:2|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 531 {"inst": "movS Rd!=XX, Rn!=XX, sop #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 532 {"inst": "movS Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|1|1111|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 533 {"inst": "movt Rx!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0110|0|immZ:4|0|immZ:3|Rx|immZ:8" , "it": "any"}, 534 {"inst": "movw Rd!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0010|0|immZ:4|0|immZ:3|Rd|immZ:8" , "it": "any"}, 535 {"inst": "mrc #CP, #op1, Rd!=XX, Cn, Cm, {#op2}" , "t32": "1110|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4" , "it": "any"}, 536 {"inst": "mrc2 #CP, #op1, Rd!=XX, Cn, Cm, {#op2}" , "t32": "1111|111|0|op1:3|1|Cn:4|Rd|CP:4|op2:3|1|Cm:4" , "it": "any"}, 537 {"inst": "mrrc #CP, #op1, Rd!=XX, Rd2!=Rd, Cm" , "t32": "1110|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4" , "it": "any"}, 538 {"inst": "mrrc2 #CP, #op1, Rd!=XX, Rd2!=Rd, Cm" , "t32": "1111|110|0010|1|Rd2|Rd|CP:4|op1:4|Cm:4" , "it": "any"}, 539 {"inst": "mrs Rd!=XX, #APSR" , "t32": "11110011111|APSR:1|1111|1000|Rd|0000|0000" , "it": "any"}, 540 {"inst": "msr #APSR, Rn!=PC" , "t32": "1111|001|1100|0|Rn|1100|APSR:2|00|0000|0000" , "it": "any"}, 541 {"inst": "mul Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|101|Rm:3|Rx:3" , "it": "in"}, 542 {"inst": "mulS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|101|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W"}, 543 {"inst": "mul Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|0|Rn|1111|Rd|0000|Rm" , "it": "any"}, 544 {"inst": "mvn Rd!=HI, Rn!=HI" , "t16": "0100|001|111|Rn:3|Rd:3" , "it": "in"}, 545 {"inst": "mvn Rd!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0011|0|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any"}, 546 {"inst": "mvn Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|0|1111|0|imm:3|Rd|imm:8" , "it": "any"}, 547 {"inst": "mvnS Rd!=HI, Rn!=HI" , "t16": "0100|001|111|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W"}, 548 {"inst": "mvnS Rd!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0011|1|1111|0|n:3|Rd|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 549 {"inst": "mvnS Rd!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|1|1111|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 550 {"inst": "nop" , "t16": "1011|111|1000|0|0000" , "it": "any"}, 551 {"inst": "nop" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0000" , "it": "any"}, 552 {"inst": "orn Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0011|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 553 {"inst": "orn Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 554 {"inst": "ornS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0011|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 555 {"inst": "ornS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0011|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 556 {"inst": "orr Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|100|Rm:3|Rx:3" , "it": "in"}, 557 {"inst": "orr Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0010|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 558 {"inst": "orr Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 559 {"inst": "orrS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|001|100|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 560 {"inst": "orrS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|0010|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 561 {"inst": "orrS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0010|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 562 {"inst": "pkhbt Rd!=XX, Rn!=XX, Rm!=XX, {lsl #n}" , "t32": "1110|101|0110|0|Rn|0|n:3|Rd|n:2|00|Rm" , "it": "any"}, 563 {"inst": "pkhtb Rd!=XX, Rn!=XX, Rm!=XX, {asr #n}" , "t32": "1110|101|0110|0|Rn|0|n:3|Rd|n:2|10|Rm" , "it": "any"}, 564 {"inst": "pld [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"}, 565 {"inst": "pld [Rn!=PC, #off]" , "t32": "1111|100|0100|1|Rn|1111|off:12" , "it": "any"}, 566 {"inst": "pld [Rn!=PC, #-off]" , "t32": "1111|100|0000|1|Rn|1111|1100|off:8" , "it": "any"}, 567 {"inst": "pld [Rn==PC, #+/-off]" , "t32": "1111|100|0U00|1|Rn|1111|off:12" , "it": "any"}, 568 {"inst": "pldw [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"}, 569 {"inst": "pldw [Rn!=PC, #off]" , "t32": "1111|100|0101|1|Rn|1111|off:12" , "it": "any"}, 570 {"inst": "pldw [Rn!=PC, #-off]" , "t32": "1111|100|0001|1|Rn|1111|1100|off:8" , "it": "any"}, 571 {"inst": "pop Rd!=SP" , "t32": "1111|100|0010|1|1101|Rd|1011|00000100" , "it": "any"}, 572 {"inst": "pop RdList" , "t16": "1011|110|immMask[15]|immMask[7:0]" , "it": "any", "imm": "GpListImm(RsList, 0x80FF)"}, 573 {"inst": "pop RdList" , "t32": "1110|100|0101|1|1101|immMask[15:14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0xDFFF)"}, 574 {"inst": "push Rs!=XX" , "t32": "1111|100|0010|0|1101|Rs|1101|0000|0100" , "it": "any"}, 575 {"inst": "push RsList" , "t16": "1011|010|immMask[14]|immMask[7:0]" , "it": "any", "imm": "GpListImm(RsList, 0x40FF)"}, 576 {"inst": "push RsList" , "t32": "1110|100|0101|0|1101|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"}, 577 {"inst": "qadd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1000|Rn" , "it": "any", "io": "Q=X"}, 578 {"inst": "qadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|0001|Rn" , "it": "any"}, 579 {"inst": "qadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|0001|Rn" , "it": "any"}, 580 {"inst": "qasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rm|1111|Rd|0001|Rn" , "it": "any"}, 581 {"inst": "qdadd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1001|Rn" , "it": "any", "io": "Q=X"}, 582 {"inst": "qdsub Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1011|Rn" , "it": "any", "io": "Q=X"}, 583 {"inst": "qsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rm|1111|Rd|0001|Rn" , "it": "any"}, 584 {"inst": "qsub Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rm|1111|Rd|1010|Rn" , "it": "any", "io": "Q=X"}, 585 {"inst": "qsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rm|1111|Rd|0001|Rn" , "it": "any"}, 586 {"inst": "qsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rm|1111|Rd|0001|Rn" , "it": "any"}, 587 {"inst": "rbit Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1010|Rn" , "it": "any"}, 588 {"inst": "rev Rd!=HI, Rn!=HI" , "t16": "1011|101|000|Rn:3|Rd:3" , "it": "any"}, 589 {"inst": "rev Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1000|Rn" , "it": "any"}, 590 {"inst": "rev16 Rd!=HI, Rn!=HI" , "t16": "1011|101|001|Rn:3|Rd:3" , "it": "any"}, 591 {"inst": "rev16 Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1001|Rn" , "it": "any"}, 592 {"inst": "revsh Rd!=HI, Rn!=HI" , "t16": "1011|101|011|Rn:3|Rd:3" , "it": "any"}, 593 {"inst": "revsh Rd!=XX, Rn!=XX" , "t32": "1111|101|0100|1|Rm|1111|Rd|1011|Rn" , "it": "any"}, 594 {"inst": "ror Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|0|1111|0|n:3|Rd|n:2|11|Rn" , "it": "any"}, 595 {"inst": "ror Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "in"}, 596 {"inst": "ror Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0011|0|Rn|1111|Rd|0000|Rm" , "it": "any"}, 597 {"inst": "rorS Rd!=XX, Rn!=XX, #n" , "t32": "1110|101|0010|1|1111|0|n:3|Rd|n:2|11|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 598 {"inst": "rorS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|111|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W"}, 599 {"inst": "rorS Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0011|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "N=W Z=W C=W"}, 600 {"inst": "rsb Rd!=HI, Rn!=HI, #zero" , "t16": "0100|001001|Rn:3|Rd:3" , "it": "in"}, 601 {"inst": "rsb Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1110|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 602 {"inst": "rsb Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1110|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 603 {"inst": "rsbS Rd!=HI, Rn!=HI, #zero" , "t16": "0100|001001|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"}, 604 {"inst": "rsbS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1110|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"}, 605 {"inst": "rsbS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1110|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 606 {"inst": "rrx Rd!=XX, Rn!=XX" , "t32": "1110|101|0010|0|1111|0000|Rd|0011|Rn" , "it": "any", "io": "C=R"}, 607 {"inst": "rrxS Rd!=XX, Rn!=XX" , "t32": "1110|101|0010|1|1111|0000|Rd|0011|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 608 {"inst": "sadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"}, 609 {"inst": "sadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"}, 610 {"inst": "sasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"}, 611 {"inst": "sbc Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|110|Rm:3|Rx:3" , "it": "in"}, 612 {"inst": "sbc Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1011|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 613 {"inst": "sbc Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1011|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 614 {"inst": "sbcS Rx!=HI, Rx!=HI, Rm!=HI" , "t16": "0100|000|110|Rm:3|Rx:3" , "it": "out", "io": "N=W Z=W C=W V=W"}, 615 {"inst": "sbcS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1011|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"}, 616 {"inst": "sbcS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1011|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 617 {"inst": "sbfx Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1010|0|Rn|0|lsb:3|Rd|lsb:2|0|widthM1:5" , "it": "any", "imm": "SbfxUbfxImm(lsb, width)"}, 618 {"inst": "sel Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|1000|Rm" , "it": "any"}, 619 {"inst": "setend #immZ" , "t16": "1011|0110|010|1|immZ:1|000" , "it": "out"}, 620 {"inst": "shadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0010|Rm" , "it": "any"}, 621 {"inst": "shadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0010|Rm" , "it": "any"}, 622 {"inst": "shasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0010|Rm" , "it": "any"}, 623 {"inst": "shsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0010|Rm" , "it": "any"}, 624 {"inst": "shsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0010|Rm" , "it": "any"}, 625 {"inst": "shsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0010|Rm" , "it": "any"}, 626 {"inst": "smlabb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"}, 627 {"inst": "smlabt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"}, 628 {"inst": "smlatb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0010|Rm" , "it": "any", "io": "Q=X"}, 629 {"inst": "smlatt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0011|Rm" , "it": "any", "io": "Q=X"}, 630 {"inst": "smlad Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|0|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"}, 631 {"inst": "smladx Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|0|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"}, 632 {"inst": "smlal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|0000|Rm" , "it": "any"}, 633 {"inst": "smlalbb RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1000|Rm" , "it": "any"}, 634 {"inst": "smlalbt RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1001|Rm" , "it": "any"}, 635 {"inst": "smlaltb RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1010|Rm" , "it": "any"}, 636 {"inst": "smlaltt RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1011|Rm" , "it": "any"}, 637 {"inst": "smlald RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1100|Rm" , "it": "any"}, 638 {"inst": "smlaldx RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|0|Rn|RxLo|RxHi|1101|Rm" , "it": "any"}, 639 {"inst": "smlawb Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"}, 640 {"inst": "smlawt Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"}, 641 {"inst": "smlsd Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "it": "any", "io": "Q=X"}, 642 {"inst": "smlsdx Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "it": "any", "io": "Q=X"}, 643 {"inst": "smlsld RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|1|Rn|RxLo|RxHi|1100|Rm" , "it": "any", "io": "Q=X"}, 644 {"inst": "smlsldx RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1110|1|Rn|RxLo|RxHi|1101|Rm" , "it": "any", "io": "Q=X"}, 645 {"inst": "smmla Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "it": "any"}, 646 {"inst": "smmlar Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "it": "any"}, 647 {"inst": "smmls Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|0|Rn|Ra|Rd|0000|Rm" , "it": "any"}, 648 {"inst": "smmlsr Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|0|Rn|Ra|Rd|0001|Rm" , "it": "any"}, 649 {"inst": "smmul Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|1|Rn|1111|Rd|0000|Rm" , "it": "any"}, 650 {"inst": "smmulr Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|1|Rn|1111|Rd|0001|Rm" , "it": "any"}, 651 {"inst": "smuad Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "Q=X"}, 652 {"inst": "smuadx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|0|Rn|1111|Rd|0001|Rm" , "it": "any", "io": "Q=X"}, 653 {"inst": "smulbb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0000|Rm" , "it": "any"}, 654 {"inst": "smulbt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0001|Rm" , "it": "any"}, 655 {"inst": "smultb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0010|Rm" , "it": "any"}, 656 {"inst": "smultt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1000|1|Rn|1111|Rd|0011|Rm" , "it": "any"}, 657 {"inst": "smull RdLo!=XX, RdHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1100|0|Rn|RdLo|RdHi|0000|Rm" , "it": "any"}, 658 {"inst": "smulwb Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|1|Rn|1111|Rd|0000|Rm" , "it": "any"}, 659 {"inst": "smulwt Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1001|1|Rn|1111|Rd|0001|Rm" , "it": "any"}, 660 {"inst": "smusd Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|0|Rn|1111|Rd|0000|Rm" , "it": "any"}, 661 {"inst": "smusdx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1010|0|Rn|1111|Rd|0001|Rm" , "it": "any"}, 662 {"inst": "ssat Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|100|00|Rn|0|000|Rd|00|0|imm:5" , "it": "any", "imm": "SsatImm(sat)", "io": "Q=X"}, 663 {"inst": "ssat Rd!=XX, #sat, Rn!=XX, lsl_or_asr #n" , "t32": "1111|001|100|sop:2|Rn|0|n:3|Rd|n:2|0|imm:5" , "it": "any", "imm": "SsatImm(sat, n)", "io": "Q=X"}, 664 {"inst": "ssat16 Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|1001|0|Rn|0000|Rd|0000|imm:4" , "it": "any", "imm": "Ssat16Imm(sat)", "io": "Q=X"}, 665 {"inst": "ssax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"}, 666 {"inst": "ssub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"}, 667 {"inst": "ssub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0000|Rm" , "it": "any", "io": "GE=W"}, 668 {"inst": "stmia [Rn!=HI]!, RsList" , "t16": "1100|0|Rn:3|immMask:8" , "it": "any", "imm": "GpListImm(RsList, 0xFF)"}, 669 {"inst": "stmia [Rn!=PC]{!}, RsList" , "t32": "1110|100|010W|0|Rn|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"}, 670 {"inst": "stmdb [Rn!=PC]{!}, RsList" , "t32": "1110|100|100W|0|Rn|0|immMask[14]|0|immMask[12:0]" , "it": "any", "imm": "GpListImm(RsList, 0x5FFF)"}, 671 {"inst": "str Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|000|Rm:3|Rn:3|Rs:3" , "it": "any"}, 672 {"inst": "str Rs!=PC, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0010|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"}, 673 {"inst": "str Rs!=HI, [Rn==SP, #off*4]" , "t16": "1001|0|Rs:3|off:8" , "it": "any"}, 674 {"inst": "str Rs!=HI, [Rn!=HI, #off*4]" , "t16": "0110|0|off:5|Rn:3|Rs:3" , "it": "any"}, 675 {"inst": "str Rs!=PC, [Rn!=PC, #off]" , "t32": "1111|100|0110|0|Rn|Rs|off:12" , "it": "any"}, 676 {"inst": "str Rs!=PC, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0010|0|Rn|Rs|1PUW|off:8" , "it": "any"}, 677 {"inst": "strb Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|010|Rm:3|Rn:3|Rs:3" , "it": "any"}, 678 {"inst": "strb Rs!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0000|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"}, 679 {"inst": "strb Rs!=HI, [Rn!=HI, #off*4]" , "t16": "0111|0|off:5|Rn:3|Rs:3" , "it": "any"}, 680 {"inst": "strb Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0100|0|Rn|Rs|off:12" , "it": "any"}, 681 {"inst": "strb Rs!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0000|0|Rn|Rs|1PUW|off:8" , "it": "any"}, 682 {"inst": "strbt Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0000|0|Rn|Rs|1110|off:8" , "it": "any"}, 683 {"inst": "strd Rs!=XX, Rs2!=XX, [Rn!=PC, #off]{@}{!}" , "t32": "1110|100|PU1W|0|Rn|Rs|Rs2|off:8" , "it": "any"}, 684 {"inst": "strex Rd!=XX, Rs!=XX, [Rn!=PC, #off]" , "t32": "1110|100|0010|0|Rn|Rs|Rd|off:8" , "it": "any", "mod": "UNPRED_COMPLEX"}, 685 {"inst": "strexb Rd!=XX, Rs!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|0100|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"}, 686 {"inst": "strexd Rd!=XX, Rs!=XX, Rs2!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|Rs2|0111|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"}, 687 {"inst": "strexh Rd!=XX, Rs!=XX, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|0101|Rd" , "it": "any", "mod": "UNPRED_COMPLEX"}, 688 {"inst": "strh Rs!=HI, [Rn!=HI, Rm!=HI]" , "t16": "0101|001|Rm:3|Rn:3|Rs:3" , "it": "any"}, 689 {"inst": "strh Rs!=XX, [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|0001|0|Rn|Rs|0|00000|n:2|Rm" , "it": "any"}, 690 {"inst": "strh Rs!=HI, [Rn!=HI, #off*4]" , "t16": "1000|0|off:5|Rn:3|Rs:3" , "it": "any"}, 691 {"inst": "strh Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0101|0|Rn|Rs|off:12" , "it": "any"}, 692 {"inst": "strh Rs!=XX, [Rn!=PC, #+/-off]{@}{!}" , "t32": "1111|100|0001|0|Rn|Rs|1PUW|off:8" , "it": "any"}, 693 {"inst": "strht Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0001|0|Rn|Rs|1110|off:8" , "it": "any"}, 694 {"inst": "strt Rs!=XX, [Rn!=PC, #off]" , "t32": "1111|100|0010|0|Rn|Rs|1110|off:8" , "it": "any"}, 695 {"inst": "sub Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|101|Rm:3|Rn:3|Rd:3" , "it": "in"}, 696 {"inst": "sub Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|111|immZ:3|Rn:3|Rd:3" , "it": "in"}, 697 {"inst": "sub Rx!=HI, Rx!=HI, #immZ" , "t16": "0011|1|Rx:3|immZ:8" , "it": "in"}, 698 {"inst": "sub Rx==SP, Rx==SP, #immZ*4" , "t16": "1011|00001|immZ:7" , "it": "any"}, 699 {"inst": "sub Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 700 {"inst": "sub Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|0|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any"}, 701 {"inst": "sub Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1101|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 702 {"inst": "sub Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1101|0|Rn|0|imm:3|Rd|imm:8" , "it": "any"}, 703 {"inst": "sub Rd!=XX, Rn!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0101|0|Rn|0|immZ:3|Rd|immZ:8" , "it": "any"}, 704 {"inst": "sub Rd!=HI, Rn!=HI, Rm!=HI" , "t16": "0001|101|Rm:3|Rn:3|Rd:3" , "it": "in"}, 705 {"inst": "subS Rd!=HI, Rn!=HI, #immZ" , "t16": "0001|111|immZ:3|Rn:3|Rd:3" , "it": "out", "io": "N=W Z=W C=W V=W"}, 706 {"inst": "subS Rx!=HI, Rx!=HI, #immZ" , "t16": "0001|1|Rx:3|immZ:8" , "it": "out", "io": "N=W Z=W C=W V=W"}, 707 {"inst": "subS Rd!=XX, Rn!=XX, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"}, 708 {"inst": "subS Rd!=PC, Rn==SP, Rm!=XX, {sop #n}" , "t32": "1110|101|1101|1|Rn|0|n:3|Rd|n:2|sop:2|Rm" , "it": "any", "io": "N=W Z=W C=W V=W"}, 709 {"inst": "subS Rd!=XX, Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 710 {"inst": "subS Rd!=PC, Rn==SP, #immA" , "t32": "1111|0|imm:1|0|1101|1|Rn|0|imm:3|Rd|imm:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 711 {"inst": "subS Rd!=XX, Rn!=XX, #immZ" , "t32": "1111|0|immZ:1|1|0101|1|Rn|0|immZ:3|Rd|immZ:8" , "it": "any", "io": "N=W Z=W C=W V=W"}, 712 {"inst": "svc #immZ" , "t16": "1101|1111|immZ:8" , "it": "any"}, 713 {"inst": "sxtab Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0010|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"}, 714 {"inst": "sxtab16 Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0001|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"}, 715 {"inst": "sxtah Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0000|0|Rn|1111|Rd|1|0|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"}, 716 {"inst": "sxtb Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|001|Rn:3|Rd:3" , "it": "any"}, 717 {"inst": "sxtb Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0010|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"}, 718 {"inst": "sxtb16 Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0001|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"}, 719 {"inst": "sxth Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|000|Rn:3|Rd:3" , "it": "any"}, 720 {"inst": "sxth Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0000|0|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"}, 721 {"inst": "tbb Rn!=SP, Rn!=XX" , "t32": "1110|100|0110|1|Rn|1111|0000|0000|Rn" , "it": "out last"}, 722 {"inst": "tbh Rn!=SP, Rn!=XX" , "t32": "1110|100|0110|1|Rn|1111|0000|0001|Rn" , "it": "out last"}, 723 {"inst": "teq Rn!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0100|1|Rn|0|n:3|1111|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 724 {"inst": "teq Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0100|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 725 {"inst": "tst Rn!=HI, Rn!=HI" , "t16": "0100|00|1000|Rn:3|Rn:3" , "it": "any", "io": "N=W Z=W C=W"}, 726 {"inst": "tst Rn!=XX, Rn!=XX, {sop #n}" , "t32": "1110|101|0000|1|Rn|0|n:3|1111|n:2|sop:2|Rn" , "it": "any", "io": "N=W Z=W C=W"}, 727 {"inst": "tst Rn!=XX, #immA" , "t32": "1111|0|imm:1|0|0000|1|Rn|0|imm:3|1111|imm:8" , "it": "any", "io": "N=W Z=W C=W"}, 728 {"inst": "uadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"}, 729 {"inst": "uadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"}, 730 {"inst": "uasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"}, 731 {"inst": "ubfx Rd!=XX, Rn!=XX, #lsb, #width" , "t32": "1111|001|1110|0|Rn|0|lsb:3|Rd|lsb:2|0|widthM1:5" , "it": "any", "imm": "SbfxUbfxImm(lsb, width)"}, 732 {"inst": "uhadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0110|Rm" , "it": "any"}, 733 {"inst": "uhadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0110|Rm" , "it": "any"}, 734 {"inst": "uhasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0110|Rm" , "it": "any"}, 735 {"inst": "uhsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0110|Rm" , "it": "any"}, 736 {"inst": "uhsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0110|Rm" , "it": "any"}, 737 {"inst": "uhsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0110|Rm" , "it": "any"}, 738 {"inst": "umaal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1111|0|Rn|RxLo|RxHi|0110|Rm" , "it": "any"}, 739 {"inst": "umlal RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1111|0|Rn|RxLo|RxHi|0000|Rm" , "it": "any"}, 740 {"inst": "umull RdLo!=XX, RdHi!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1101|0|Rn|RdLo|RdHi|0000|Rm" , "it": "any"}, 741 {"inst": "uqadd16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|1|Rn|1111|Rd|0101|Rm" , "it": "any"}, 742 {"inst": "uqadd8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0100|0|Rn|1111|Rd|0101|Rm" , "it": "any"}, 743 {"inst": "uqasx Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0101|0|Rn|1111|Rd|0101|Rm" , "it": "any"}, 744 {"inst": "uqsax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0101|Rm" , "it": "any"}, 745 {"inst": "uqsub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0101|Rm" , "it": "any"}, 746 {"inst": "uqsub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0101|Rm" , "it": "any"}, 747 {"inst": "usad8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1011|1|Rn|1111|Rd|0000|Rm" , "it": "any"}, 748 {"inst": "usada8 Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "t32": "1111|101|1011|1|Rn|Ra|Rd|0000|Rm" , "it": "any"}, 749 {"inst": "usat Rd!=XX, #sat, Rn!=XX, {lsl_or_asr #n}" , "t32": "1111|001|110|sop:2|Rn|0|n:3|Rd|n:2|0|sat:5" , "it": "any", "io": "Q=X"}, 750 {"inst": "usat16 Rd!=XX, #sat, Rn!=XX" , "t32": "1111|001|1101|0|Rn|0000|Rd|0000|sat:4" , "it": "any", "io": "Q=X"}, 751 {"inst": "usax Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0111|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"}, 752 {"inst": "usub16 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|1|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"}, 753 {"inst": "usub8 Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|0110|0|Rn|1111|Rd|0100|Rm" , "it": "any", "io": "GE=W"}, 754 {"inst": "uxtab Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0010|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"}, 755 {"inst": "uxtab16 Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0001|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"}, 756 {"inst": "uxtah Rd!=XX, Rn!=XX, Rm!=XX, {ror #n}" , "t32": "1111|101|0000|1|Rn|1111|Rd|10|imm:2|Rm" , "it": "any", "imm": "Ror8Imm(n)"}, 757 {"inst": "uxtb Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|011|Rn:3|Rd:3" , "it": "any"}, 758 {"inst": "uxtb Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0010|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"}, 759 {"inst": "uxtb16 Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0001|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"}, 760 {"inst": "uxth Rd!=HI, Rn!=HI, {ror #zero}" , "t16": "1011|001|010|Rn:3|Rd:3" , "it": "any"}, 761 {"inst": "uxth Rd!=XX, Rn!=XX, {ror #n}" , "t32": "1111|101|0000|1|1111|1111|Rd|10|imm:2|Rn" , "it": "any", "imm": "Ror8Imm(n)"}, 762 {"inst": "wfe" , "t16": "1011|1111|0010|0000" , "it": "any"}, 763 {"inst": "wfe" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0010" , "it": "any"}, 764 {"inst": "wfi" , "t16": "1011|1111|0011|0000" , "it": "any"}, 765 {"inst": "wfi" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0011" , "it": "any"}, 766 {"inst": "yield" , "t16": "1011|1111|0001|0000" , "it": "any"}, 767 {"inst": "yield" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0001" , "it": "any"} 768 ]}, 769 770 {"category": "GP GP_EXT", "level": "ARMv7+", "data": [ 771 {"inst": "clrex" , "a32": "1111|010|1011|1|1111|1111|0000|0001|1111"}, 772 {"inst": "dbg #immZ" , "a32": "cond|001|1001|0|0000|1111|0000|1111|immZ:4" , "ext": "ARMv8-"}, 773 {"inst": "dmb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0101|immZ:4"}, 774 {"inst": "dsb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0100|immZ:4"}, 775 {"inst": "isb #immZ" , "a32": "1111|010|1011|1|1111|1111|0000|0110|immZ:4"}, 776 {"inst": "pldw [Rn!=PC, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|1U00|1|Rn|1111|n:5|sop:2|0|Rm" , "ext": "MP"}, 777 {"inst": "pldw [Rn!=PC, #+/-off]" , "a32": "1111|010|1U00|1|Rn|1111|off:12" , "ext": "MP"}, 778 {"inst": "pli [Rn, +/-Rm!=PC, {sop #n}]" , "a32": "1111|011|0U10|1|Rn|1111|n:5|sop:2|0|Rm"}, 779 {"inst": "pli [Rn, #+/-off]" , "a32": "1111|010|0U10|1|Rn|1111|off:12"}, 780 {"inst": "sev" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0100"}, 781 {"inst": "sevl" , "a32": "cond|001|1001|0|0000|1111|0000|0000|0101"} 782 ]}, 783 784 {"category": "GP GP_EXT", "level": "ARMv7+", "data": [ 785 {"inst": "clrex" , "t32": "1111|001|1101|1|1111|1000|1111|0010|1111" , "it": "any"}, 786 {"inst": "dmb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0101|immZ:4" , "it": "any"}, 787 {"inst": "dsb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0100|immZ:4" , "it": "any"}, 788 {"inst": "ldrexb Rd!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|0100|1111" , "it": "any"}, 789 {"inst": "ldrexd Rd!=XX, Rd2!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|Rd2 |0111|1111" , "it": "any"}, 790 {"inst": "ldrexh Rd!=XX, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|0101|1111" , "it": "any"}, 791 {"inst": "isb #immZ" , "t32": "1111|001|1101|1|1111|1000|1111|0110|immZ:4" , "it": "any"}, 792 {"inst": "pli [Rn!=PC, Rm!=XX, {lsl #n}]" , "t32": "1111|100|1000|1|Rn|1111|0000|00|n:2|Rm" , "it": "any"}, 793 {"inst": "pli [Rn!=PC, #off]" , "t32": "1111|100|1100|1|Rn|1111|off:12" , "it": "any"}, 794 {"inst": "pli [Rn!=PC, #-off]" , "t32": "1111|100|1000|1|Rn|1111|1100|off:8" , "it": "any"}, 795 {"inst": "pli [Rn==PC, #+/-off]" , "t32": "1111|100|1U00|1|Rn|1111|off:12" , "it": "any"}, 796 {"inst": "sev" , "t16": "1011|1111|0100|0000" , "it": "any"}, 797 {"inst": "sev" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0000" , "it": "any"}, 798 {"inst": "sevl" , "t16": "1011|1111|0101|0000" , "it": "any"}, 799 {"inst": "sevl" , "t32": "1111|001|1101|0|1111|1000|0000|0000|0101" , "it": "any"} 800 ]}, 801 802 {"category": "GP GP_EXT", "level": "ARMv8+", "data": [ 803 {"inst": "lda Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1100|1001|1111"}, 804 {"inst": "ldab Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1100|1001|1111"}, 805 {"inst": "ldaex Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1100|1|Rn|Rd|1110|1001|1111"}, 806 {"inst": "ldaexb Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1110|1|Rn|Rd|1110|1001|1111"}, 807 {"inst": "ldaexd Rd<=13, Rd2+, [Rn!=PC]" , "a32": "cond|000|1101|1|Rn|Rd|1110|1001|1111"}, 808 {"inst": "ldaexh Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1110|1001|1111"}, 809 {"inst": "ldah Rd!=PC, [Rn!=PC]" , "a32": "cond|000|1111|1|Rn|Rd|1100|1001|1111"}, 810 {"inst": "stl Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|1111|1100|1001|Rs"}, 811 {"inst": "stlb Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|1111|1100|1001|Rs"}, 812 {"inst": "stlex Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1100|0|Rn|Rd|1110|1001|Rs"}, 813 {"inst": "stlexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1110|0|Rn|Rd|1110|1001|Rs"}, 814 {"inst": "stlexd Rd!=PC, Rs!=PC, Rs2+, [Rn!=PC]" , "a32": "cond|000|1101|0|Rn|Rd|1110|1001|Rs"}, 815 {"inst": "stlexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|Rd|1110|1001|Rs"}, 816 {"inst": "stlh Rs!=PC, [Rn!=PC]" , "a32": "cond|000|1111|0|Rn|1111|1100|1001|Rs"} 817 ]}, 818 819 {"category": "GP GP_EXT", "level": "ARMv8+", "data": [ 820 {"inst": "dcps1" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0001" , "it": "out"}, 821 {"inst": "dcps2" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0010" , "it": "out"}, 822 {"inst": "dcps3" , "t32": "1111|011|1100|0|1111|1000|0000|0000|0011" , "it": "out"}, 823 {"inst": "lda Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1010|1111" , "it": "any"}, 824 {"inst": "ldab Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1000|1111" , "it": "any"}, 825 {"inst": "ldaex Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1110|1111" , "it": "any"}, 826 {"inst": "ldaexb Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1100|1111" , "it": "any"}, 827 {"inst": "ldaexd Rd!=PC, Rd2!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|Rd2|1111|1111" , "it": "any"}, 828 {"inst": "ldaexh Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1101|1111" , "it": "any"}, 829 {"inst": "ldah Rd!=PC, [Rn!=PC]" , "t32": "1110|100|0110|1|Rn|Rd|1111|1001|1111" , "it": "any"}, 830 {"inst": "stl Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1010|1111" , "it": "any"}, 831 {"inst": "stlb Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1000|1111" , "it": "any"}, 832 {"inst": "stlex Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1110|Rd" , "it": "any"}, 833 {"inst": "stlexb Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1100|Rd" , "it": "any"}, 834 {"inst": "stlexd Rd!=PC, Rs!=PC, Rs2!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|Rs2|1111|Rd" , "it": "any"}, 835 {"inst": "stlexh Rd!=PC, Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1101|Rd" , "it": "any"}, 836 {"inst": "stlh Rs!=PC, [Rn!=PC]" , "t32": "1110|100|0110|0|Rn|Rs|1111|1001|1111" , "it": "any"} 837 ]}, 838 839 {"category": "GP GP_EXT", "ext": "IDIVA", "data": [ 840 {"inst": "sdiv Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1000|1|Rd|1111|Rm|0001|Rn"}, 841 {"inst": "udiv Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|011|1001|1|Rd|1111|Rm|0001|Rn"} 842 ]}, 843 844 {"category": "GP GP_EXT", "ext": "IDIVT", "data": [ 845 {"inst": "sdiv Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1100|1|Rn|1111|Rd|1111|Rm" , "it": "any"}, 846 {"inst": "udiv Rd!=XX, Rn!=XX, Rm!=XX" , "t32": "1111|101|1101|1|Rn|1111|Rd|1111|Rm" , "it": "any"} 847 ]}, 848 849 {"category": "GP GP_EXT", "data": [ 850 {"inst": "csdb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0100"}, 851 {"inst": "ssbb" , "a32": "1111|010|1011|1|1111|1111|0000|0100|0000"}, 852 {"inst": "pssbb" , "a32": "1111|010|1011|1|1111|1111|0000|0100|0100"} 853 ]}, 854 855 {"category": "GP GP_EXT", "data": [ 856 {"inst": "csdb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0100" , "it": "out"}, 857 {"inst": "ssbb" , "t32": "1111|001|1101|1|1111|1000|1111|0100|0000" , "it": "any"}, 858 {"inst": "pssbb" , "t32": "1111|001|1101|1|1111|1000|1111|0100|0100" , "it": "any"} 859 ]}, 860 861 {"category": "GP GP_EXT", "ext": "CLRBHB", "data": [ 862 {"inst": "clrbhb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0110"} 863 ]}, 864 865 {"category": "GP GP_EXT", "ext": "CLRBHB", "data": [ 866 {"inst": "clrbhb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0110" , "it": "any"} 867 ]}, 868 869 {"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [ 870 {"inst": "crc32b Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rn|Rd|0000|0100|Rm"}, 871 {"inst": "crc32h Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rn|Rd|0000|0100|Rm"}, 872 {"inst": "crc32w Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rn|Rd|0000|0100|Rm"}, 873 {"inst": "crc32cb Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1000|0|Rn|Rd|0010|0100|Rm"}, 874 {"inst": "crc32ch Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1001|0|Rn|Rd|0010|0100|Rm"}, 875 {"inst": "crc32cw Rd!=PC, Rn!=PC, Rm!=PC" , "a32": "cond|000|1010|0|Rn|Rd|0010|0100|Rm"} 876 ]}, 877 878 {"category": "GP GP_EXT CRYPTO_HASH", "ext": "CRC32", "data": [ 879 {"inst": "crc32b Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|00|Rm" , "it": "out"}, 880 {"inst": "crc32h Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|01|Rm" , "it": "out"}, 881 {"inst": "crc32w Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|0|Rn|1111|Rd|10|10|Rm" , "it": "out"}, 882 {"inst": "crc32cb Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|00|Rm" , "it": "out"}, 883 {"inst": "crc32ch Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|01|Rm" , "it": "out"}, 884 {"inst": "crc32cw Rd!=PC, Rn!=PC, Rm!=PC" , "t32": "1111|101|0110|1|Rn|1111|Rd|10|10|Rm" , "it": "out"} 885 ]}, 886 887 {"category": "GP GP_EXT", "ext": "PAN", "data": [ 888 {"inst": "setpan #immZ" , "a32": "1111|000|1000|1|0000|0000|00|immZ:1|0|0000|0000"} 889 ]}, 890 891 {"category": "GP GP_EXT", "ext": "PAN", "data": [ 892 {"inst": "setpan #immZ" , "t16": "1011|0110|0001|immZ:1|000" , "it": "out"} 893 ]}, 894 895 {"category": "GP GP_EXT", "ext": "RAS", "data": [ 896 {"inst": "esb" , "a32": "cond|001|1001|0|0000|1111|0000|0001|0000"} 897 ]}, 898 899 {"category": "GP GP_EXT", "ext": "RAS", "data": [ 900 {"inst": "esb" , "t32": "1111|001|1101|0|1111|1000|0000|0001|0000" , "it": "any"} 901 ]}, 902 903 {"category": "GP GP_EXT", "ext": "SB", "data": [ 904 {"inst": "sb" , "a32": "1111|010|1011|1|1111|1111|0000|0111|0000"} 905 ]}, 906 907 {"category": "GP GP_EXT", "ext": "SB", "data": [ 908 {"inst": "sb" , "t32": "1111|001|1101|1|1111|1000|1111|0111|0000" , "it": "out"} 909 ]}, 910 911 {"category": "GP GP_EXT", "ext": "SECURITY", "data": [ 912 {"inst": "smc #immZ" , "a32": "cond|000|1011|0|000000000000|0111|immZ:4"} 913 ]}, 914 915 {"category": "GP GP_EXT", "ext": "SECURITY", "data": [ 916 {"inst": "smc #immZ" , "t32": "1111|011|1111|1|immZ:4|1000|000000000000" , "it": "any"} 917 ]}, 918 919 {"category": "FP", "ext": "FP", "data": [ 920 {"inst": "vabs.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|00|Vd|10|10|1|1|'Vn|0|Vn"}, 921 {"inst": "vabs.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|00|00|Vd|10|11|1|1|Vn'|0|Vn"}, 922 {"inst": "vadd.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|11|Vn|Vd|1010|'Vn|0|'Vm|0|Vm"}, 923 {"inst": "vadd.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|11|Vn|Vd|1011|Vn'|0|Vm'|0|Vm"}, 924 {"inst": "vcmp.f32 Sn, Sm" , "a32": "cond|11101|'Vn|11|01|00|Vn|10|10|01|'Vm|0|Vm"}, 925 {"inst": "vcmp.f32 Sn, #zero" , "a32": "cond|11101|'Vn|11|01|01|Vn|10|10|01|00|0000"}, 926 {"inst": "vcmp.f64 Dn, Dm" , "a32": "cond|11101|Vn'|11|01|00|Vn|10|11|01|Vm'|0|Vm"}, 927 {"inst": "vcmp.f64 Dn, #zero" , "a32": "cond|11101|Vn'|11|01|01|Vn|10|11|01|00|0000"}, 928 {"inst": "vcmpe.f32 Sn, Sm" , "a32": "cond|11101|'Vn|11|01|00|Vn|10|10|11|'Vm|0|Vm"}, 929 {"inst": "vcmpe.f32 Sn, #zero" , "a32": "cond|11101|'Vn|11|01|01|Vn|10|10|11|00|0000"}, 930 {"inst": "vcmpe.f64 Dn, Dm" , "a32": "cond|11101|Vn'|11|01|00|Vn|10|11|11|Vm'|0|Vm"}, 931 {"inst": "vcmpe.f64 Dn, #zero" , "a32": "cond|11101|Vn'|11|01|01|Vn|10|11|11|00|0000"}, 932 {"inst": "vcvt.f32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|01|11|Vd|10111|1|Vn'|0|Vn"}, 933 {"inst": "vcvt.f64.f32 Dd, Sn" , "a32": "cond|11101|Vd'|11|01|11|Vd|10101|1|'Vn|0|Vn"}, 934 {"inst": "vcvt.f32.s32 Sd, Sn" , "a32": "cond|11101|'Vd|11|10|00|Vd|10101|1|'Vn|0|Vn"}, 935 {"inst": "vcvt.f32.u32 Sd, Sn" , "a32": "cond|11101|'Vd|11|10|00|Vd|10100|1|'Vn|0|Vn"}, 936 {"inst": "vcvt.f64.s32 Dd, Sn" , "a32": "cond|11101|Vd'|11|10|00|Vd|10111|1|'Vn|0|Vn"}, 937 {"inst": "vcvt.f64.u32 Dd, Sn" , "a32": "cond|11101|Vd'|11|10|00|Vd|10110|1|'Vn|0|Vn"}, 938 {"inst": "vcvt.f32.s16 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 939 {"inst": "vcvt.s16.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 940 {"inst": "vcvt.f32.u16 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 941 {"inst": "vcvt.u16.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 942 {"inst": "vcvt.f32.s32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 943 {"inst": "vcvt.s32.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 944 {"inst": "vcvt.f32.u32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|10|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 945 {"inst": "vcvt.u32.f32 Sx, Sx, #fbits" , "a32": "cond|11101|'Vx|11|11|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 946 {"inst": "vcvt.f64.s16 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 947 {"inst": "vcvt.s16.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 948 {"inst": "vcvt.f64.u16 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 949 {"inst": "vcvt.u16.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(16, fbits)"}, 950 {"inst": "vcvt.f64.s32 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 951 {"inst": "vcvt.s32.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 952 {"inst": "vcvt.f64.u32 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|10|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 953 {"inst": "vcvt.u32.f64 Dx, Dx, #fbits" , "a32": "cond|11101|Vx'|11|11|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "imm": "VecFBitsVFP(32, fbits)"}, 954 {"inst": "vcvtr.s32.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn"}, 955 {"inst": "vcvtr.s32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn"}, 956 {"inst": "vcvtr.u32.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn"}, 957 {"inst": "vcvtr.u32.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn"}, 958 {"inst": "vdiv.f32 Sd, Sn, Sm" , "a32": "cond|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm"}, 959 {"inst": "vdiv.f64 Dd, Dn, Dm" , "a32": "cond|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm"}, 960 {"inst": "vldr.32 Sd, [Rn, #+/-off*4]" , "a32": "cond|1101U|'Vd|01|Rn|Vd|1010|off:8"}, 961 {"inst": "vldr.64 Dd, [Rn, #+/-off*4]" , "a32": "cond|1101U|Vd'|01|Rn|Vd|1011|off:8"}, 962 {"inst": "vmla.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|00|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm"}, 963 {"inst": "vmla.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|00|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm"}, 964 {"inst": "vmls.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|00|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm"}, 965 {"inst": "vmls.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|00|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm"}, 966 {"inst": "vmov.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0000|Vd|1010|0|1|'Vn|0|Vn"}, 967 {"inst": "vmov.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0000|Vd|1011|0|1|Vn'|0|Vn"}, 968 {"inst": "vmov.f32 Sd, #immVFP" , "a32": "cond|11101|'Vd|11|imm:4|Vd|1010|0000|imm:4" , "imm": "VecVFPImm(immVFP)"}, 969 {"inst": "vmov.f64 Dd, #immVFP" , "a32": "cond|11101|Vd'|11|imm:4|Vd|1011|0000|imm:4" , "imm": "VecVFPImm(immVFP)"}, 970 {"inst": "vmul.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm"}, 971 {"inst": "vmul.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm"}, 972 {"inst": "vneg.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0001|Vd|10|10|01|'Vn|0|Vn"}, 973 {"inst": "vneg.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0001|Vd|10|11|01|Vn'|0|Vn"}, 974 {"inst": "vnmla.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm"}, 975 {"inst": "vnmla.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm"}, 976 {"inst": "vnmls.f32 Sx, Sn, Sm" , "a32": "cond|11100|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm"}, 977 {"inst": "vnmls.f64 Dx, Dn, Dm" , "a32": "cond|11100|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm"}, 978 {"inst": "vnmul.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|10|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm"}, 979 {"inst": "vnmul.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|10|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm"}, 980 {"inst": "vsqrt.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|0001|Vd|10|10|11|'Vn|0|Vn"}, 981 {"inst": "vsqrt.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|0001|Vd|10|11|11|Vn'|0|Vn"}, 982 {"inst": "vstr.32 Ss, [Rn, #+/-off*4]" , "a32": "cond|1101U|'Vs|00|Rn|Vs|1010|off:8"}, 983 {"inst": "vstr.64 Ds, [Rn, #+/-off*4]" , "a32": "cond|1101U|Vs'|00|Rn|Vs|1011|off:8"}, 984 {"inst": "vsub.f32 Sd, Sn, Sm" , "a32": "cond|11100|'Vd|11|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm"}, 985 {"inst": "vsub.f64 Dd, Dn, Dm" , "a32": "cond|11100|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm"} 986 ]}, 987 988 {"category": "FP", "ext": "FP", "data": [ 989 {"inst": "vabs.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|00|Vd|10|10|1|1|'Vn|0|Vn" , "it": "any"}, 990 {"inst": "vabs.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|00|00|Vd|10|11|1|1|Vn'|0|Vn" , "it": "any"}, 991 {"inst": "vadd.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|1010|'Vn|0|'Vm|0|Vm" , "it": "any"}, 992 {"inst": "vadd.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|11|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "it": "any"}, 993 {"inst": "vcmp.f32 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|10|01|'Vm|0|Vm" , "it": "any"}, 994 {"inst": "vcmp.f32 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|10|01|00|0000" , "it": "any"}, 995 {"inst": "vcmp.f64 Dn, Dm" , "t32": "1110|11101|Vn'|11|01|00|Vn|10|11|01|Vm'|0|Vm" , "it": "any"}, 996 {"inst": "vcmp.f64 Dn, #zero" , "t32": "1110|11101|Vn'|11|01|01|Vn|10|11|01|00|0000" , "it": "any"}, 997 {"inst": "vcmpe.f32 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|10|11|'Vm|0|Vm" , "it": "any"}, 998 {"inst": "vcmpe.f32 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|10|11|00|0000" , "it": "any"}, 999 {"inst": "vcmpe.f64 Dn, Dm" , "t32": "1110|11101|Vn'|11|01|00|Vn|10|11|11|Vm'|0|Vm" , "it": "any"}, 1000 {"inst": "vcmpe.f64 Dn, #zero" , "t32": "1110|11101|Vn'|11|01|01|Vn|10|11|11|00|0000" , "it": "any"}, 1001 {"inst": "vcvt.f32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10111|1|Vn'|0|Vn" , "it": "any"}, 1002 {"inst": "vcvt.f64.f32 Dd, Sn" , "t32": "1110|11101|Vd'|11|01|11|Vd|10101|1|'Vn|0|Vn" , "it": "any"}, 1003 {"inst": "vcvt.f32.s32 Sd, Sn" , "t32": "1110|11101|'Vd|11|10|00|Vd|10101|1|'Vn|0|Vn" , "it": "any"}, 1004 {"inst": "vcvt.f32.u32 Sd, Sn" , "t32": "1110|11101|'Vd|11|10|00|Vd|10100|1|'Vn|0|Vn" , "it": "any"}, 1005 {"inst": "vcvt.f64.s32 Dd, Sn" , "t32": "1110|11101|Vd'|11|10|00|Vd|10111|1|'Vn|0|Vn" , "it": "any"}, 1006 {"inst": "vcvt.f64.u32 Dd, Sn" , "t32": "1110|11101|Vd'|11|10|00|Vd|10110|1|'Vn|0|Vn" , "it": "any"}, 1007 {"inst": "vcvt.f32.s16 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1008 {"inst": "vcvt.s16.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|10|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1009 {"inst": "vcvt.f32.u16 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1010 {"inst": "vcvt.u16.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|11|Vx|10100|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1011 {"inst": "vcvt.f32.s32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1012 {"inst": "vcvt.s32.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|10|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1013 {"inst": "vcvt.f32.u32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|10|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1014 {"inst": "vcvt.u32.f32 Sx, Sx, #fbits" , "t32": "1110|11101|'Vx|11|11|11|Vx|10101|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1015 {"inst": "vcvt.f64.s16 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1016 {"inst": "vcvt.s16.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|10|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1017 {"inst": "vcvt.f64.u16 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1018 {"inst": "vcvt.u16.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|11|Vx|10110|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(16, fbits)"}, 1019 {"inst": "vcvt.f64.s32 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1020 {"inst": "vcvt.s32.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|10|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1021 {"inst": "vcvt.f64.u32 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|10|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1022 {"inst": "vcvt.u32.f64 Dx, Dx, #fbits" , "t32": "1110|11101|Vx'|11|11|11|Vx|10111|1|imm[0]|0|imm[4:1]" , "it": "any", "imm": "VecFBitsVFP(32, fbits)"}, 1023 {"inst": "vcvtr.s32.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "it": "any"}, 1024 {"inst": "vcvtr.s32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "it": "any"}, 1025 {"inst": "vcvtr.u32.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "it": "any"}, 1026 {"inst": "vcvtr.u32.f64 Sd, Dn" , "t32": "1110|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "it": "any"}, 1027 {"inst": "vdiv.f32 Sd, Sn, Sm" , "t32": "1110|11101|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"}, 1028 {"inst": "vdiv.f64 Dd, Dn, Dm" , "t32": "1110|11101|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"}, 1029 {"inst": "vldr.32 Sd, [Rn, #+/-off*4]" , "t32": "1110|1101U|'Vd|01|Rn|Vd|1010|off:8" , "it": "any"}, 1030 {"inst": "vldr.64 Dd, [Rn, #+/-off*4]" , "t32": "1110|1101U|Vd'|01|Rn|Vd|1011|off:8" , "it": "any"}, 1031 {"inst": "vmla.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|00|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"}, 1032 {"inst": "vmls.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|00|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"}, 1033 {"inst": "vmov.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0000|Vd|1010|0|1|'Vn|0|Vn" , "it": "any"}, 1034 {"inst": "vmov.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0000|Vd|1011|0|1|Vn'|0|Vn" , "it": "any"}, 1035 {"inst": "vmov.f32 Sd, #immVFP" , "t32": "1110|11101|'Vd|11|imm:4|Vd|1010|0000|imm:4" , "it": "any", "imm": "VecVFPImm(immVFP)"}, 1036 {"inst": "vmov.f64 Dd, #immVFP" , "t32": "1110|11101|Vd'|11|imm:4|Vd|1011|0000|imm:4" , "it": "any", "imm": "VecVFPImm(immVFP)"}, 1037 {"inst": "vmul.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"}, 1038 {"inst": "vmul.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"}, 1039 {"inst": "vneg.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|10|01|'Vn|0|Vn" , "it": "any"}, 1040 {"inst": "vneg.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0001|Vd|10|11|01|Vn'|0|Vn" , "it": "any"}, 1041 {"inst": "vnmla.f32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"}, 1042 {"inst": "vnmla.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|01|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"}, 1043 {"inst": "vnmls.f32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "it": "any"}, 1044 {"inst": "vnmls.f64 Dx, Dn, Dm" , "t32": "1110|11100|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any"}, 1045 {"inst": "vnmul.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"}, 1046 {"inst": "vnmul.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|10|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"}, 1047 {"inst": "vsqrt.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|10|11|'Vn|0|Vn" , "it": "any"}, 1048 {"inst": "vsqrt.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|0001|Vd|1011|1|1|Vn'|0|Vn" , "it": "any"}, 1049 {"inst": "vstr.32 Ss, [Rn, #+/-off*4]" , "t32": "1110|1101U|'Vs|00|Rn|Vs|1010|off:8" , "it": "any"}, 1050 {"inst": "vstr.64 Ds, [Rn, #+/-off*4]" , "t32": "1110|1101U|Vs'|00|Rn|Vs|1011|off:8" , "it": "any"}, 1051 {"inst": "vsub.f32 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "it": "any"}, 1052 {"inst": "vsub.f64 Dd, Dn, Dm" , "t32": "1110|11100|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "it": "any"} 1053 ]}, 1054 1055 {"category": "FP", "ext": "FP FP16", "data": [ 1056 {"inst": "vabs.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|00|00|Vd|10|01|1|1|'Vn|0|Vn"}, 1057 {"inst": "vadd.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|11|Vn|Vd|1001|'Vn|0|'Vm|0|Vm"}, 1058 {"inst": "vcmp.f16 Sn, Sm" , "a32": "1110|11101|'Vn|11|01|00|Vn|10|01|01|'Vm|0|Vm"}, 1059 {"inst": "vcmp.f16 Sn, #zero" , "a32": "1110|11101|'Vn|11|01|01|Vn|10|01|01|00|0000"}, 1060 {"inst": "vcmpe.f16 Sn, Sm" , "a32": "1110|11101|'Vn|11|01|00|Vn|10|01|11|'Vm|0|Vm"}, 1061 {"inst": "vcmpe.f16 Sn, #zero" , "a32": "1110|11101|'Vn|11|01|01|Vn|10|01|11|00|0000"}, 1062 {"inst": "vdiv.f16 Sd, Sn, Sm" , "a32": "1110|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm"}, 1063 {"inst": "vldr.16 Sd, [Rn, #+/-off*2]" , "a32": "1110|1101U|'Vd|01|Rn|Vd|1001|off:8"}, 1064 {"inst": "vmla.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|00|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm"}, 1065 {"inst": "vmls.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|00|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm"}, 1066 {"inst": "vmov.f16 Rd!=PC, Sn" , "a32": "1110|11100|0|01|Vn|Rd|1001|'Vn|00|1|0000"}, 1067 {"inst": "vmov.f16 Sd, Rn!=PC" , "a32": "1110|11100|0|00|Vd|Rn|1001|'Vd|00|1|0000"}, 1068 {"inst": "vmov.f16 Sd, #immVFP" , "a32": "1110|11101|'Vd|11|imm:4|Vd|1001|0000|imm:4" , "imm": "VecVFPImm(immVFP)"}, 1069 {"inst": "vmovx.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|00|00|Vd|1010|01|'Vn|0|Vn"}, 1070 {"inst": "vmul.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm"}, 1071 {"inst": "vmul.f16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3"}, 1072 {"inst": "vmul.f16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3"}, 1073 {"inst": "vneg.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|0001|Vd|10|01|01|'Vn|0|Vn"}, 1074 {"inst": "vnmla.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm"}, 1075 {"inst": "vnmls.f16 Sx, Sn, Sm" , "a32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm"}, 1076 {"inst": "vnmul.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm"}, 1077 {"inst": "vsqrt.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|0001|Vd|10|01|11|'Vn|0|Vn"}, 1078 {"inst": "vstr.16 Ss, [Rn, #+/-off*2]" , "a32": "1110|1101U|'Vs|00|Rn|Vs|1001|off:8"}, 1079 {"inst": "vsub.f16 Sd, Sn, Sm" , "a32": "1110|11100|'Vd|11|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm"} 1080 ]}, 1081 1082 {"category": "FP", "ext": "FP FP16", "data": [ 1083 {"inst": "vabs.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|00|00|Vd|10|01|1|1|'Vn|0|Vn" , "it": "out"}, 1084 {"inst": "vadd.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|1001|'Vn|0|'Vm|0|Vm" , "it": "out"}, 1085 {"inst": "vcmp.f16 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|01|01|'Vm|0|Vm" , "it": "out"}, 1086 {"inst": "vcmp.f16 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|01|01|00|0000" , "it": "out"}, 1087 {"inst": "vcmpe.f16 Sn, Sm" , "t32": "1110|11101|'Vn|11|01|00|Vn|10|01|11|'Vm|0|Vm" , "it": "out"}, 1088 {"inst": "vcmpe.f16 Sn, #zero" , "t32": "1110|11101|'Vn|11|01|01|Vn|10|01|11|00|0000" , "it": "out"}, 1089 {"inst": "vdiv.f16 Sd, Sn, Sm" , "t32": "1110|11101|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"}, 1090 {"inst": "vldr.16 Sd, [Rn, #+/-off*2]" , "t32": "1110|1101U|'Vd|01|Rn|Vd|1001|off:8" , "it": "out"}, 1091 {"inst": "vmla.f16-32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|00|Vn|Vx|10|sz|'Vn|0|'Vm|0|Vm" , "it": "out"}, 1092 {"inst": "vmls.f16-32 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|00|Vn|Vx|10|sz|'Vn|1|'Vm|0|Vm" , "it": "out"}, 1093 {"inst": "vmov.f16 Rd!=PC, Sn" , "t32": "1110|11100|0|01|Vn|Rd|1001|'Vn|00|1|0000" , "it": "out"}, 1094 {"inst": "vmov.f16 Sd, Rn!=PC" , "t32": "1110|11100|0|00|Vd|Rn|1001|'Vd|00|1|0000" , "it": "out"}, 1095 {"inst": "vmov.f16 Sd, #immVFP" , "t32": "1110|11101|'Vd|11|imm:4|Vd|1001|0000|imm:4" , "it": "out", "imm": "VecVFPImm(immVFP)"}, 1096 {"inst": "vmovx.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|00|00|Vd|1010|01|'Vn|0|Vn" , "it": "out"}, 1097 {"inst": "vmul.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"}, 1098 {"inst": "vmul.f16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"}, 1099 {"inst": "vmul.f16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1001|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"}, 1100 {"inst": "vneg.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|01|01|'Vn|0|Vn" , "it": "out"}, 1101 {"inst": "vnmla.f16 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"}, 1102 {"inst": "vnmls.f16 Sx, Sn, Sm" , "t32": "1110|11100|'Vx|01|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "it": "out"}, 1103 {"inst": "vnmul.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|10|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"}, 1104 {"inst": "vsqrt.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|0001|Vd|10|01|11|'Vn|0|Vn" , "it": "out"}, 1105 {"inst": "vstr.16 Ss, [Rn, #+/-off*2]" , "t32": "1110|1101U|'Vs|00|Rn|Vs|1001|off:8" , "it": "out"}, 1106 {"inst": "vsub.f16 Sd, Sn, Sm" , "t32": "1110|11100|'Vd|11|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "it": "out"} 1107 ]}, 1108 1109 {"category": "ASIMD", "ext": "VFPv4", "data": [ 1110 {"inst": "vfma.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4 FP16"}, 1111 {"inst": "vfma.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|10|Vn|Vx|10|10|'Vn|0|'Vm|0|Vm" , "ext": "VFPv4"}, 1112 {"inst": "vfma.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|10|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "ext": "VFPv4"}, 1113 {"inst": "vfms.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|10|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4 FP16"}, 1114 {"inst": "vfms.f32 Sx, Sn, Sm" , "a32": "cond|11101|'Vx|10|Vn|Vx|10|10|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4"}, 1115 {"inst": "vfms.f64 Dx, Dn, Dm" , "a32": "cond|11101|Vx'|10|Vn|Vx|10|11|Vn'|1|Vm'|0|Vm" , "ext": "VFPv4"}, 1116 {"inst": "vfnma.f16 Sx, Sn, Sm" , "a32": "1110|11101|'Vx|01|Vn|Vx|10|01|'Vn|1|'Vm|0|Vm" , "ext": "VFPv4 FP16"}, 1117 {"inst": "vfnma.f32 Sx, Sn, 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{"inst": "vfnms.f64 Dx, Dn, Dm" , "t32": "1110|11101|Vx'|01|Vn|Vx|10|11|Vn'|0|Vm'|0|Vm" , "it": "any", "ext": "VFPv4"} 1137 ]}, 1138 1139 {"category": "ASIMD", "ext": "ASIMD", "data": [ 1140 {"inst": "vaba.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1141 {"inst": "vaba.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1142 {"inst": "vabal.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1143 {"inst": "vabd.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1144 {"inst": "vabd.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1145 {"inst": "vabd.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1146 {"inst": "vabd.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1147 {"inst": "vabd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1148 {"inst": "vabd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1149 {"inst": "vabdl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1150 {"inst": "vabs.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1151 {"inst": "vabs.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1152 {"inst": "vabs.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1153 {"inst": "vabs.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1154 {"inst": "vabs.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1155 {"inst": "vabs.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1156 {"inst": "vacge.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1157 {"inst": "vacge.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1158 {"inst": "vacge.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1159 {"inst": "vacge.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1160 {"inst": "vacgt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1161 {"inst": "vacgt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1162 {"inst": "vacgt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1163 {"inst": "vacgt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1164 {"inst": "vacle.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1165 {"inst": "vacle.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1166 {"inst": "vacle.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"}, 1167 {"inst": "vacle.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"}, 1168 {"inst": "vaclt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1169 {"inst": "vaclt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1170 {"inst": "vaclt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"}, 1171 {"inst": "vaclt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"}, 1172 {"inst": "vadd.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1173 {"inst": "vadd.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1174 {"inst": "vadd.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1175 {"inst": "vadd.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1176 {"inst": "vadd.x8-64 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1177 {"inst": "vadd.x8-64 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1178 {"inst": "vaddhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00101|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 1179 {"inst": "vaddl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1180 {"inst": "vaddw.x8-32 Vd, Vn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1181 {"inst": "vand.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1182 {"inst": "vand.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1183 {"inst": "vand.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"}, 1184 {"inst": "vand.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"}, 1185 {"inst": "vbic.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1186 {"inst": "vbic.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1187 {"inst": "vbic.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 1188 {"inst": "vbic.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 1189 {"inst": "vbif.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1190 {"inst": "vbif.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1191 {"inst": "vbit.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1192 {"inst": "vbit.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1193 {"inst": "vbsl.any Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1194 {"inst": "vbsl.any Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1195 {"inst": "vceq.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1196 {"inst": "vceq.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1197 {"inst": "vceq.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1198 {"inst": "vceq.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1199 {"inst": "vceq.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1200 {"inst": "vceq.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1201 {"inst": "vceq.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1202 {"inst": "vceq.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1203 {"inst": "vceq.x8-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1204 {"inst": "vceq.x8-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1205 {"inst": "vceq.x8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00010|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1206 {"inst": "vceq.x8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00010|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1207 {"inst": "vcge.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1208 {"inst": "vcge.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1209 {"inst": "vcge.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1210 {"inst": "vcge.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1211 {"inst": "vcge.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1212 {"inst": "vcge.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1213 {"inst": "vcge.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1214 {"inst": "vcge.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1215 {"inst": "vcge.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1216 {"inst": "vcge.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1217 {"inst": "vcge.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00001|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1218 {"inst": "vcge.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00001|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1219 {"inst": "vcgt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1220 {"inst": "vcgt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1221 {"inst": "vcgt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1222 {"inst": "vcgt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1223 {"inst": "vcgt.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1224 {"inst": "vcgt.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1225 {"inst": "vcgt.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1226 {"inst": "vcgt.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1227 {"inst": "vcgt.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1228 {"inst": "vcgt.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1229 {"inst": "vcgt.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00000|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1230 {"inst": "vcgt.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00000|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1231 {"inst": "vcle.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1232 {"inst": "vcle.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1233 {"inst": "vcle.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1234 {"inst": "vcle.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1235 {"inst": "vcle.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1236 {"inst": "vcle.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1237 {"inst": "vcle.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1238 {"inst": "vcle.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1239 {"inst": "vcle.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"}, 1240 {"inst": "vcle.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"}, 1241 {"inst": "vcle.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00011|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1242 {"inst": "vcle.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00011|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1243 {"inst": "vcls.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1244 {"inst": "vcls.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1245 {"inst": "vclt.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1246 {"inst": "vclt.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1247 {"inst": "vclt.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1248 {"inst": "vclt.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1249 {"inst": "vclt.f16 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1250 {"inst": "vclt.f16 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|01|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1251 {"inst": "vclt.f32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1252 {"inst": "vclt.f32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|10|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1253 {"inst": "vclt.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1254 {"inst": "vclt.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1255 {"inst": "vclt.s8-32 Dd, Dn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00100|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1256 {"inst": "vclt.s8-32 Vd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|01|Vd|00100|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1257 {"inst": "vclz.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1258 {"inst": "vclz.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1259 {"inst": "vcnt.x8 Dd, Dn" , "a32": "1111|00111|Vd'|11|00|00|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1260 {"inst": "vcnt.x8 Vd, Vn" , "a32": "1111|00111|Vd'|11|00|00|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1261 {"inst": "vcvt.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01110|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1262 {"inst": "vcvt.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01110|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1263 {"inst": "vcvt.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01111|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1264 {"inst": "vcvt.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01111|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1265 {"inst": "vcvt.f32.s32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1266 {"inst": "vcvt.f32.s32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1267 {"inst": "vcvt.f32.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01101|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1268 {"inst": "vcvt.f32.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01101|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1269 {"inst": "vcvt.f32.s32 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1270 {"inst": "vcvt.f32.s32 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1271 {"inst": "vcvt.s32.f32 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1272 {"inst": "vcvt.s32.f32 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1273 {"inst": "vcvt.f32.u32 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1274 {"inst": "vcvt.f32.u32 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1275 {"inst": "vcvt.u32.f32 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1276 {"inst": "vcvt.u32.f32 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1277 {"inst": "vcvta.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1278 {"inst": "vcvta.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1279 {"inst": "vcvta.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1280 {"inst": "vcvta.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1281 {"inst": "vcvtm.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00110|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1282 {"inst": "vcvtm.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1283 {"inst": "vcvtm.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00111|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1284 {"inst": "vcvtm.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1285 {"inst": "vcvtm.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1286 {"inst": "vcvtm.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1287 {"inst": "vcvtm.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1288 {"inst": "vcvtm.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1289 {"inst": "vcvtn.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00010|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1290 {"inst": "vcvtn.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00010|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1291 {"inst": "vcvtn.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00011|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1292 {"inst": "vcvtn.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00011|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1293 {"inst": "vcvtn.s32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1294 {"inst": "vcvtn.s32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1295 {"inst": "vcvtn.u32.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1296 {"inst": "vcvtn.u32.f64 Sd, Dn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1297 {"inst": "vcvtp.s32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00100|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1298 {"inst": "vcvtp.s32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00100|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1299 {"inst": "vcvtp.u32.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00101|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1300 {"inst": "vcvtp.u32.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|00101|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1301 {"inst": "vcvtp.s32.f32 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"vmin.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1468 {"inst": "vmin.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1469 {"inst": "vmin.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1470 {"inst": "vminnm.f16 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|01|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+ FP16"}, 1471 {"inst": "vminnm.f32 Sd, Sn, Sm" , "a32": "1111|11101|'Vd|00|Vn|Vd|10|10|'Vn|1|'Vm|0|Vm" , "ext": "ARMv8+"}, 1472 {"inst": "vminnm.f64 Dd, Dn, Dm" , "a32": "1111|11101|Vd'|00|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ARMv8+"}, 1473 {"inst": "vminnm.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1474 {"inst": "vminnm.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1475 {"inst": "vminnm.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1476 {"inst": "vminnm.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1477 {"inst": "vmla.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1478 {"inst": "vmla.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1479 {"inst": "vmla.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1480 {"inst": "vmla.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1481 {"inst": "vmla.x8-32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1482 {"inst": "vmla.x8-32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1483 {"inst": "vmla.f16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"}, 1484 {"inst": "vmla.f16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0001|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "FP16"}, 1485 {"inst": "vmla.f32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1486 {"inst": "vmla.f32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1487 {"inst": "vmla.x16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1488 {"inst": "vmla.x16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1489 {"inst": "vmla.x32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1490 {"inst": "vmla.x32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1491 {"inst": "vmlal.x8-32 Vx, Dn, Dm" , "a32": "1111|001U1|Vx'|sz|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1492 {"inst": "vmlal.x16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vx'|01|Vn|Vx|0010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"}, 1493 {"inst": "vmlal.x32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vx'|10|Vn|Vx|0010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1494 {"inst": "vmls.f16 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1495 {"inst": "vmls.f16 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1496 {"inst": "vmls.f32 Dx, Dn, Dm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1497 {"inst": "vmls.f32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1498 {"inst": "vmls.x8-32 Dx, Dn, Dm" , "a32": "1111|00110|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1499 {"inst": "vmls.x8-32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|sz|Vn|Vx|1001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1500 {"inst": "vmls.f16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1501 {"inst": "vmls.f16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1502 {"inst": "vmls.f32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1503 {"inst": "vmls.f32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1504 {"inst": "vmls.x16 Dx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1505 {"inst": "vmls.x16 Vx, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1506 {"inst": "vmls.x32 Dx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1507 {"inst": "vmls.x32 Vx, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1508 {"inst": "vmlsl.x8-32 Vx, Dn, Dm" , "a32": "1111|001U1|Vx'|sz|Vn|Vx|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1509 {"inst": "vmlsl.x16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vx'|01|Vn|Vx|0110|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"}, 1510 {"inst": "vmlsl.x32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vx'|10|Vn|Vx|0110|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1511 {"inst": "vmov Rd!=PC, Sn" , "a32": "cond|11100|0|01|Vn|Rd|1010|'Vn|00|1|0000" , "ext": "ASIMD"}, 1512 {"inst": "vmov Sd, Rn!=PC" , "a32": "cond|11100|0|00|Vd|Rn|1010|'Vd|00|1|0000" , "ext": "ASIMD"}, 1513 {"inst": "vmov Rd!=PC, Rd2!=PC, Ss!=31, Ss2+" , "a32": "cond|11000|1|01|Rd2|Rd|101|000|'Vs|1|Vs" , "ext": "ASIMD"}, 1514 {"inst": "vmov Sd!=31, Sd2+, Rs!=PC, Rs2!=PC" , "a32": "cond|11000|1|00|Rs2|Rs|101|000|'Vd|1|Vd" , "ext": "ASIMD"}, 1515 {"inst": "vmov Rd!=PC, Rd2!=PC, Ds" , "a32": "cond|11000|1|01|Rd2|Rd|1011|0|0|Vs'|1|Vs" , "ext": "ASIMD"}, 1516 {"inst": "vmov Dd, Rs!=PC, Rs2!=PC" , "a32": "cond|11000|1|00|Rs2|Rs|1011|0|0|Vd'|1|Vd" , "ext": "ASIMD"}, 1517 {"inst": "vmov.x8 Dd[#i], Rn!=PC" , "a32": "cond|11100|1|i:1|0|Vd|Rn|1011|Vd'|i:2|1|0000" , "ext": "ASIMD"}, 1518 {"inst": "vmov.x16 Dd[#i], Rn!=PC" , "a32": "cond|11100|0|i:1|0|Vd|Rn|1011|Vd'|i:1|110000" , "ext": "ASIMD"}, 1519 {"inst": "vmov.x32 Dd[#i], Rn!=PC" , "a32": "cond|11100|0|i:1|0|Vd|Rn|1011|Vd'|001|0000" , "ext": "ASIMD"}, 1520 {"inst": "vmov.x8 Rd!=PC, Dn[#i]" , "a32": "cond|1110U|1|i:1|1|Vn|Rd|1011|Vn'|i:2|1|0000" , "ext": "ASIMD"}, 1521 {"inst": "vmov.x16 Rd!=PC, Dn[#i]" , "a32": "cond|1110U|0|i:1|1|Vn|Rd|1011|Vn'|i:1|110000" , "ext": "ASIMD"}, 1522 {"inst": "vmov.x32 Rd!=PC, Dn[#i]" , "a32": "cond|11100|0|i:1|1|Vn|Rd|1011|Vn'|001|0000" , "ext": "ASIMD"}, 1523 {"inst": "vmov.any Dd, Dn" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"}, 1524 {"inst": "vmov.any Vd, Vn" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"}, 1525 {"inst": "vmov.x8-64 Dd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"}, 1526 {"inst": "vmov.x8-64 Vd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"}, 1527 {"inst": "vmovl.x8 Vd, Dn" , "a32": "1111|001U1|Vd'|00|1000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"}, 1528 {"inst": "vmovl.x16 Vd, Dn" , "a32": "1111|001U1|Vd'|01|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"}, 1529 {"inst": "vmovl.x32 Vd, Dn" , "a32": "1111|001U1|Vd'|10|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"}, 1530 {"inst": "vmovn.x16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"}, 1531 {"inst": "vmul.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1532 {"inst": "vmul.f16 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1533 {"inst": "vmul.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1534 {"inst": "vmul.f32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1535 {"inst": "vmul.x8-32|p8 Dd, Dn, Dm" , "a32": "1111|001P0|Vd'|sz|Vn|Vd|1001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1536 {"inst": "vmul.x8-32|p8 Vd, Vn, Vm" , "a32": "1111|001P0|Vd'|sz|Vn|Vd|1001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1537 {"inst": "vmul.f32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1538 {"inst": "vmul.f32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1539 {"inst": "vmul.x16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1540 {"inst": "vmul.x16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 1541 {"inst": "vmul.x32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1542 {"inst": "vmul.x32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 1543 {"inst": "vmull.x8-32|p8 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1544 {"inst": "vmull.p64 Vd, Dn, Dm" , "a32": "1111|00101|Vd'|10|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1545 {"inst": "vmull.x16 Vd, Dn, Dm<=07[#i]" , "a32": "1111|001U1|Vd'|01|Vn|Vd|1010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"}, 1546 {"inst": "vmull.x32 Vd, Dn, Dm<=15[#i]" , "a32": "1111|001U1|Vd'|10|Vn|Vd|1010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1547 {"inst": "vmvn.any Dd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"}, 1548 {"inst": "vmvn.any Vd, #immV" , "a32": "1111|001|imm:1|1|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"}, 1549 {"inst": "vmvn.any Dd, Dn" , "a32": "1111|00111|Vd'|11|0000|Vd|0101|10|Vn'|0|Vn" , "ext": "ASIMD"}, 1550 {"inst": "vmvn.any Vd, Vn" , "a32": "1111|00111|Vd'|11|0000|Vd|0101|11|Vn'|0|Vn" , "ext": "ASIMD"}, 1551 {"inst": "vneg.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1552 {"inst": "vneg.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1553 {"inst": "vneg.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD"}, 1554 {"inst": "vneg.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD"}, 1555 {"inst": "vneg.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|0011|10|Vn'|0|Vn" , "ext": "ASIMD"}, 1556 {"inst": "vneg.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|01|Vd|0011|11|Vn'|0|Vn" , "ext": "ASIMD"}, 1557 {"inst": "vorn.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"}, 1558 {"inst": "vorn.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"}, 1559 {"inst": "vorn.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1560 {"inst": "vorn.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1561 {"inst": "vorr.x16-64 Dx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 1562 {"inst": "vorr.x16-64 Vx, #immV" , "a32": "1111|001|imm:1|1|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 1563 {"inst": "vorr.any Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1564 {"inst": "vorr.any Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1565 {"inst": "vpadal.x8-32 Dx, Dn" , "a32": "1111|00111|Vx'|11|sz|00|Vx|0110|U|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1566 {"inst": "vpadal.x8-32 Vx, Vn" , "a32": "1111|00111|Vx'|11|sz|00|Vx|0110|U|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1567 {"inst": "vpadd.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1568 {"inst": "vpadd.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1569 {"inst": "vpaddl.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0010|U|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1570 {"inst": "vpaddl.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0010|U|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1571 {"inst": "vpmax.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1572 {"inst": "vpmax.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1573 {"inst": "vpmax.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1574 {"inst": "vpmin.f16 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1575 {"inst": "vpmin.f32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1576 {"inst": "vpmin.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1577 {"inst": "vpop.32 SdList" , "a32": "cond|11001|immVd[0]|11|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"}, 1578 {"inst": "vpop.64 DdList" , "a32": "cond|11001|immVd[4]|11|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"}, 1579 {"inst": "vpush.32 SdList" , "a32": "cond|11010|immVd[0]|10|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"}, 1580 {"inst": "vpush.64 DdList" , "a32": "cond|11010|immVd[4]|10|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"}, 1581 {"inst": "vqabs.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|0|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1582 {"inst": "vqabs.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1583 {"inst": "vqadd.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1584 {"inst": "vqadd.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1585 {"inst": "vqdmlal.s16-32 Vx, Dn, Dm" , "a32": "1111|00101|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1586 {"inst": "vqdmlal.s16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1587 {"inst": "vqdmlal.s32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1588 {"inst": "vqdmlsl.s16-32 Vx, Dn, Dm" , "a32": "1111|00101|Vx'|sz|Vn|Vx|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1589 {"inst": "vqdmlsl.s16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vx'|01|Vn|Vx|0111|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1590 {"inst": "vqdmlsl.s32 Vx, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vx'|10|Vn|Vx|0111|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1591 {"inst": "vqdmulh.s16-32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1592 {"inst": "vqdmulh.s16-32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1593 {"inst": "vqdmulh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1594 {"inst": "vqdmulh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1595 {"inst": "vqdmulh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1596 {"inst": "vqdmulh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1597 {"inst": "vqdmull.s16-32 Vd, Dn, Dm" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1598 {"inst": "vqdmull.s16 Vd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1599 {"inst": "vqdmull.s32 Vd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 1600 {"inst": "vqmovn.x16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1|U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 1601 {"inst": "vqmovun.s16-64 Dd, Vn" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 1602 {"inst": "vqneg.s8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|1|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1603 {"inst": "vqneg.s8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0111|1|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1604 {"inst": "vqrdmulh.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1605 {"inst": "vqrdmulh.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1606 {"inst": "vqrdmulh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1607 {"inst": "vqrdmulh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1608 {"inst": "vqrdmulh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1609 {"inst": "vqrdmulh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1610 {"inst": "vqrshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1611 {"inst": "vqrshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1612 {"inst": "vqrshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 1613 {"inst": "vqrshrn.x16-64 Dd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|1001|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 1614 {"inst": "vqrshrun.s16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 1615 {"inst": "vqrshrun.s16-64 Dd, Vn, #n" , "a32": "1111|00111|Vd'|imm:6|Vd|1000|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 1616 {"inst": "vqshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1617 {"inst": "vqshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1618 {"inst": "vqshl.x8-64 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0111|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 1619 {"inst": "vqshl.x8-64 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0111|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 1620 {"inst": "vqshlu.s8-64 Dd, Dn, #n" , "a32": "1111|00111|Vd'|imm[5:0]|Vd|0110|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 1621 {"inst": "vqshlu.s8-64 Vd, Vn, #n" , "a32": "1111|00111|Vd'|imm[5:0]|Vd|0110|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 1622 {"inst": "vqshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 1623 {"inst": "vqshrn.x16-64 Dd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|1001|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 1624 {"inst": "vqshrun.s16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 1625 {"inst": "vqshrun.s16-64 Dd, Vn, #n" , "a32": "1111|00111|Vd'|imm:6|Vd|1000|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 1626 {"inst": "vqsub.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1627 {"inst": "vqsub.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 1628 {"inst": "vraddhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 1629 {"inst": "vrecpe.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1630 {"inst": "vrecpe.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1631 {"inst": "vrecpe.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1632 {"inst": "vrecpe.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1633 {"inst": "vrecpe.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0100|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1634 {"inst": "vrecpe.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|0100|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1635 {"inst": "vrecps.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1636 {"inst": "vrecps.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1637 {"inst": "vrecps.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1638 {"inst": "vrecps.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1639 {"inst": "vrev16.x8 Dd, Dn" , "a32": "1111|00111|Vd'|11|00|00|Vd|0001|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1640 {"inst": "vrev16.x8 Vd, Vn" , "a32": "1111|00111|Vd'|11|00|00|Vd|0001|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1641 {"inst": "vrev32.x8-16 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|1|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1642 {"inst": "vrev32.x8-16 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|1|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1643 {"inst": "vrev64.x8-32 Dd, Dn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1644 {"inst": "vrev64.x8-32 Vd, Vn" , "a32": "1111|00111|Vd'|11|sz|00|Vd|0000|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1645 {"inst": "vrhadd.x8-32 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1646 {"inst": "vrhadd.x8-32 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vn|Vd|0001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1647 {"inst": "vrinta.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|00|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 1648 {"inst": "vrinta.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|00|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"}, 1649 {"inst": "vrinta.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|00|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1650 {"inst": "vrinta.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1651 {"inst": "vrinta.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1652 {"inst": "vrinta.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+"}, 1653 {"inst": "vrinta.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1654 {"inst": "vrintm.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 1655 {"inst": "vrintm.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"}, 1656 {"inst": "vrintm.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1657 {"inst": "vrintm.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1658 {"inst": "vrintm.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1659 {"inst": "vrintm.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+"}, 1660 {"inst": "vrintm.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+"}, 1661 {"inst": "vrintn.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|01|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 1662 {"inst": "vrintn.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|01|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"}, 1663 {"inst": "vrintn.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|01|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1664 {"inst": "vrintn.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1665 {"inst": "vrintn.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1666 {"inst": "vrintn.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+"}, 1667 {"inst": "vrintn.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1668 {"inst": "vrintp.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 1669 {"inst": "vrintp.f32 Sd, Sn" , "a32": "1111|11101|'Vd|11|10|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"}, 1670 {"inst": "vrintp.f64 Dd, Dn" , "a32": "1111|11101|Vd'|11|10|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1671 {"inst": "vrintp.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1672 {"inst": "vrintp.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1673 {"inst": "vrintp.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+"}, 1674 {"inst": "vrintp.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+"}, 1675 {"inst": "vrintr.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 1676 {"inst": "vrintr.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"}, 1677 {"inst": "vrintr.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1678 {"inst": "vrintx.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 1679 {"inst": "vrintx.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+"}, 1680 {"inst": "vrintx.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 1681 {"inst": "vrintx.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1682 {"inst": "vrintx.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1683 {"inst": "vrintx.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+"}, 1684 {"inst": "vrintx.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+"}, 1685 {"inst": "vrintz.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|01|10|Vd|10|01|11|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 1686 {"inst": "vrintz.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|01|10|Vd|10|10|11|'Vn|0|Vn" , "ext": "ARMv8+"}, 1687 {"inst": "vrintz.f64 Dd, Dn" , "a32": "cond|11101|Vd'|11|01|10|Vd|10|11|11|Vn'|0|Vn" , "ext": "ARMv8+"}, 1688 {"inst": "vrintz.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1689 {"inst": "vrintz.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 1690 {"inst": "vrintz.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+"}, 1691 {"inst": "vrintz.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+"}, 1692 {"inst": "vrshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1693 {"inst": "vrshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1694 {"inst": "vrshr.x8-32 Dd, Dn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"}, 1695 {"inst": "vrshr.x8-32 Vd, Vn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"}, 1696 {"inst": "vrshr.x8-32 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|0010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1697 {"inst": "vrshr.x8-32 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm:6|Vd|0010|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1698 {"inst": "vrshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|00111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow", "pseudoOf": "vmovn"}, 1699 {"inst": "vrshrn.x16-64 Dd, Vn, #n" , "a32": "1111|00101|Vd'|imm:6|Vd|1000|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 1700 {"inst": "vrsqrte.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1701 {"inst": "vrsqrte.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1702 {"inst": "vrsqrte.f32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD"}, 1703 {"inst": "vrsqrte.f32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD"}, 1704 {"inst": "vrsqrte.u32 Dd, Dn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|00|10|Vn'|0|Vn" , "ext": "ASIMD"}, 1705 {"inst": "vrsqrte.u32 Vd, Vn" , "a32": "1111|00111|Vd'|11|10|11|Vd|01|00|11|Vn'|0|Vn" , "ext": "ASIMD"}, 1706 {"inst": "vrsqrts.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1707 {"inst": "vrsqrts.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1708 {"inst": "vrsqrts.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1709 {"inst": "vrsqrts.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1710 {"inst": "vrsra.x8-64 Dx, Dn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0011|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1711 {"inst": "vrsra.x8-64 Vx, Vn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0011|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1712 {"inst": "vrsubhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 1713 {"inst": "vseleq.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"}, 1714 {"inst": "vseleq.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"}, 1715 {"inst": "vseleq.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"}, 1716 {"inst": "vselge.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"}, 1717 {"inst": "vselge.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"}, 1718 {"inst": "vselge.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"}, 1719 {"inst": "vselgt.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|11|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"}, 1720 {"inst": "vselgt.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|11|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"}, 1721 {"inst": "vselgt.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"}, 1722 {"inst": "vselvs.f16 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|01|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16"}, 1723 {"inst": "vselvs.f32 Sd, Sn, Sm" , "a32": "1111|11100|'Vd|01|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+"}, 1724 {"inst": "vselvs.f64 Dd, Dn, Dm" , "a32": "1111|11100|Vd'|01|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+"}, 1725 {"inst": "vshl.x8-64 Dd, Dn, Dm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1726 {"inst": "vshl.x8-64 Vd, Vn, Vm" , "a32": "1111|001U0|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1727 {"inst": "vshl.x8-64 Dd, Dn, #n" , "a32": "1111|00101|Vd'|imm[5:0]|Vd|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 1728 {"inst": "vshl.x8-64 Vd, Vn, #n" , "a32": "1111|00101|Vd'|imm[5:0]|Vd|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 1729 {"inst": "vshll.x8-32 Vd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)", "vecOp": "widen"}, 1730 {"inst": "vshr.x8-64 Dd, Dn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"}, 1731 {"inst": "vshr.x8-64 Vd, Vn, #zero" , "a32": "1111|00100|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "pseudoOf": "vorr"}, 1732 {"inst": "vshr.x8-64 Dd, Dn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0000|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1733 {"inst": "vshr.x8-64 Vd, Vn, #n" , "a32": "1111|001U1|Vd'|imm[5:0]|Vd|0000|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1734 {"inst": "vshrn.x16-64 Dd, Vn, #zero" , "a32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow"}, 1735 {"inst": "vshrn.x16-64 Dd, Vn, #n" , "a32": "1111|00101|Vd'|imm:6|Vd|1000|00|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 1736 {"inst": "vsli.x8-64 Dx, Dn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 1737 {"inst": "vsli.x8-64 Vx, Vn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 1738 {"inst": "vsra.x8-64 Dx, Dn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0001|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1739 {"inst": "vsra.x8-64 Vx, Vn, #n" , "a32": "1111|001U1|Vx'|imm[5:0]|Vx|0001|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1740 {"inst": "vsri.x8-64 Dx, Dn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0100|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1741 {"inst": "vsri.x8-64 Vx, Vn, #n" , "a32": "1111|00111|Vx'|imm[5:0]|Vx|0100|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 1742 {"inst": "vst1.8-64 Ds, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|1111" , "ext": "ASIMD"}, 1743 {"inst": "vst1.8-64 Ds, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|Rm" , "ext": "ASIMD"}, 1744 {"inst": "vst1.8-64 Ds, [Rn!=PC, #off==8]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0111|sz|0|align:1|1101" , "ext": "ASIMD"}, 1745 {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|1111" , "ext": "ASIMD"}, 1746 {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|Rm" , "ext": "ASIMD"}, 1747 {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1010|sz|0|align:1|1101" , "ext": "ASIMD"}, 1748 {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|1111" , "ext": "ASIMD"}, 1749 {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|Rm" , "ext": "ASIMD"}, 1750 {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0110|sz|0|align:1|1101" , "ext": "ASIMD"}, 1751 {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|1111" , "ext": "ASIMD"}, 1752 {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|Rm" , "ext": "ASIMD"}, 1753 {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0010|sz|0|align:1|1101" , "ext": "ASIMD"}, 1754 {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|1111" , "ext": "ASIMD"}, 1755 {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|Rm" , "ext": "ASIMD"}, 1756 {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1000|sz|align:2|1101" , "ext": "ASIMD"}, 1757 {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|1111" , "ext": "ASIMD"}, 1758 {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|Rm" , "ext": "ASIMD"}, 1759 {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, #off==16]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|1001|sz|align:2|1101" , "ext": "ASIMD"}, 1760 {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|1111" , "ext": "ASIMD"}, 1761 {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|Rm" , "ext": "ASIMD"}, 1762 {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0011|sz|align:2|1101" , "ext": "ASIMD"}, 1763 {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|1111" , "ext": "ASIMD"}, 1764 {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|Rm" , "ext": "ASIMD"}, 1765 {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0100|sz|0|align:1|1101" , "ext": "ASIMD"}, 1766 {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|1111" , "ext": "ASIMD"}, 1767 {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|Rm" , "ext": "ASIMD"}, 1768 {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, #off==24]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0101|sz|1|align:1|1101" , "ext": "ASIMD"}, 1769 {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|1111" , "ext": "ASIMD"}, 1770 {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|Rm" , "ext": "ASIMD"}, 1771 {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0000|sz|align:2|1101" , "ext": "ASIMD"}, 1772 {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC]" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|1111" , "ext": "ASIMD"}, 1773 {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|Rm" , "ext": "ASIMD"}, 1774 {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, #off==32]@" , "a32": "1111|01000|Vs'|00|Rn|Vs|0001|sz|align:2|1101" , "ext": "ASIMD"}, 1775 {"inst": "vstmdb.32 [Rn]!, SdList" , "a32": "cond|11010|immVd[0]|10|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"}, 1776 {"inst": "vstmdb.64 [Rn]!, DdList" , "a32": "cond|11010|immVd[4]|10|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"}, 1777 {"inst": "vstmia.32 [Rn!=PC]{!}, SdList" , "a32": "cond|11001|immVd[0]|W0|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"}, 1778 {"inst": "vstmia.64 [Rn!=PC]{!}, DdList" , "a32": "cond|11001|immVd[4]|W0|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"}, 1779 {"inst": "vstmia.32 [Rn==PC], SdList" , "a32": "cond|11001|immVd[0]|00|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "imm": "VecSListImm(SdList)"}, 1780 {"inst": "vstmia.64 [Rn==PC], DdList" , "a32": "cond|11001|immVd[4]|00|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "imm": "VecDListImm(SdList)"}, 1781 {"inst": "vsub.f16 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|11|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1782 {"inst": "vsub.f16 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|11|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1783 {"inst": "vsub.f32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|10|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1784 {"inst": "vsub.f32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|10|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1785 {"inst": "vsub.x8-64 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1786 {"inst": "vsub.x8-64 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1787 {"inst": "vsubhn.x16-64 Dd, Vn, Vm" , "a32": "1111|00101|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 1788 {"inst": "vsubl.x8-32 Vd, Dn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1789 {"inst": "vsubw.x8-32 Vd, Vn, Dm" , "a32": "1111|001U1|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1790 {"inst": "vswp.any Dx, Dx2!=Dx" , "a32": "1111|00111|Vx'|11|00|10|Vx|0000|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 1791 {"inst": "vswp.any Vx, Vx2!=Vx" , "a32": "1111|00111|Vx'|11|00|10|Vx|0000|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"}, 1792 {"inst": "vtbl.x8 Dd, Dn, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1793 {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1794 {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|10|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1795 {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1796 {"inst": "vtbx.x8 Dd, Dn, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1797 {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1798 {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|10|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1799 {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "a32": "1111|00111|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1800 {"inst": "vtrn.x8-32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 1801 {"inst": "vtrn.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"}, 1802 {"inst": "vtst.x8-32 Dd, Dn, Dm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1803 {"inst": "vtst.x8-32 Vd, Vn, Vm" , "a32": "1111|00100|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1804 {"inst": "vuzp.x8-16 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 1805 {"inst": "vuzp.x32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"}, 1806 {"inst": "vuzp.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"}, 1807 {"inst": "vzip.x8-16 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 1808 {"inst": "vzip.x32 Dx, Dx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"}, 1809 {"inst": "vzip.x8-32 Vx, Vx2" , "a32": "1111|00111|Vx'|11|sz|10|Vx|0001|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"} 1810 ]}, 1811 1812 {"category": "ASIMD", "ext": "ASIMD", "data": [ 1813 {"inst": "vaba.x8-32 Dd, Dn, Dm" , "t32": "111U|111U0|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1814 {"inst": "vaba.x8-32 Vd, Vn, Vm" , "t32": "111U|111U0|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1815 {"inst": "vabal.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1816 {"inst": "vabd.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1817 {"inst": "vabd.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1818 {"inst": "vabd.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1819 {"inst": "vabd.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1820 {"inst": "vabd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1821 {"inst": "vabd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0111|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1822 {"inst": "vabdl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1823 {"inst": "vabs.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1824 {"inst": "vabs.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1825 {"inst": "vabs.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|01|Vd|01|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1826 {"inst": "vabs.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|01|Vd|01|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1827 {"inst": "vabs.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00|11|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1828 {"inst": "vabs.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00|11|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1829 {"inst": "vacge.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1830 {"inst": "vacge.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1831 {"inst": "vacge.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1832 {"inst": "vacge.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1833 {"inst": "vacgt.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1834 {"inst": "vacgt.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1835 {"inst": "vacgt.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1836 {"inst": "vacgt.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1837 {"inst": "vacle.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1838 {"inst": "vacle.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1839 {"inst": "vacle.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"}, 1840 {"inst": "vacle.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"}, 1841 {"inst": "vaclt.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1842 {"inst": "vaclt.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD FP16"}, 1843 {"inst": "vaclt.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"}, 1844 {"inst": "vaclt.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"}, 1845 {"inst": "vadd.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1846 {"inst": "vadd.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1847 {"inst": "vadd.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1848 {"inst": "vadd.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1849 {"inst": "vadd.x8-64 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1850 {"inst": "vadd.x8-64 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1851 {"inst": "vaddhn.x16-64 Dd, Vn, Vm" , "t32": "1110|11111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 1852 {"inst": "vaddl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1853 {"inst": "vaddw.x8-32 Vd, Vn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 1854 {"inst": "vand.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1855 {"inst": "vand.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1856 {"inst": "vand.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"}, 1857 {"inst": "vand.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vbic"}, 1858 {"inst": "vbic.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1859 {"inst": "vbic.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1860 {"inst": "vbic.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0011|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 1861 {"inst": "vbic.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0111|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 1862 {"inst": "vbif.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1863 {"inst": "vbif.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1864 {"inst": "vbit.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1865 {"inst": "vbit.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1866 {"inst": "vbsl.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1867 {"inst": "vbsl.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1868 {"inst": "vceq.f16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1869 {"inst": "vceq.f16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1870 {"inst": "vceq.f16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1871 {"inst": "vceq.f16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1872 {"inst": "vceq.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1873 {"inst": "vceq.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1874 {"inst": "vceq.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1875 {"inst": "vceq.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1876 {"inst": "vceq.x8-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1877 {"inst": "vceq.x8-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1878 {"inst": "vceq.x8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00010|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1879 {"inst": "vceq.x8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00010|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1880 {"inst": "vcge.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1881 {"inst": "vcge.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1882 {"inst": "vcge.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1883 {"inst": "vcge.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1884 {"inst": "vcge.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1885 {"inst": "vcge.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1886 {"inst": "vcge.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1887 {"inst": "vcge.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1888 {"inst": "vcge.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1889 {"inst": "vcge.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1890 {"inst": "vcge.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00001|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1891 {"inst": "vcge.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00001|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1892 {"inst": "vcgt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1893 {"inst": "vcgt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 1894 {"inst": "vcgt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1895 {"inst": "vcgt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1110|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1896 {"inst": "vcgt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1897 {"inst": "vcgt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1898 {"inst": "vcgt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1899 {"inst": "vcgt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1900 {"inst": "vcgt.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1901 {"inst": "vcgt.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1902 {"inst": "vcgt.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00000|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1903 {"inst": "vcgt.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00000|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1904 {"inst": "vcle.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1905 {"inst": "vcle.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1906 {"inst": "vcle.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1907 {"inst": "vcle.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1908 {"inst": "vcle.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1909 {"inst": "vcle.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1910 {"inst": "vcle.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01011|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1911 {"inst": "vcle.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01011|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1912 {"inst": "vcle.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD"}, 1913 {"inst": "vcle.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD"}, 1914 {"inst": "vcle.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00011|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1915 {"inst": "vcle.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00011|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1916 {"inst": "vcls.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01000|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1917 {"inst": "vcls.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01000|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1918 {"inst": "vclt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1919 {"inst": "vclt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|11|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1920 {"inst": "vclt.f16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1921 {"inst": "vclt.f16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|10|Vm|Vd|1110|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1922 {"inst": "vclt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1923 {"inst": "vclt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|01|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 1924 {"inst": "vclt.f16-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1925 {"inst": "vclt.f16-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|10|01|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1926 {"inst": "vclt.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1927 {"inst": "vclt.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0011|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1928 {"inst": "vclt.s8-32 Dd, Dn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00100|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1929 {"inst": "vclt.s8-32 Vd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|01|Vd|00100|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1930 {"inst": "vclz.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01001|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1931 {"inst": "vclz.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|01001|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1932 {"inst": "vcnt.x8 Dd, Dn" , "t32": "1111|11111|Vd'|11|00|00|Vd|01010|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1933 {"inst": "vcnt.x8 Vd, Vn" , "t32": "1111|11111|Vd'|11|00|00|Vd|01010|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1934 {"inst": "vcvt.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01110|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1935 {"inst": "vcvt.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01110|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1936 {"inst": "vcvt.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01111|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1937 {"inst": "vcvt.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01111|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1938 {"inst": "vcvt.f32.s32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01100|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1939 {"inst": "vcvt.f32.s32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01100|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1940 {"inst": "vcvt.f32.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01101|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1941 {"inst": "vcvt.f32.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01101|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1942 {"inst": "vcvt.f32.s32 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1943 {"inst": "vcvt.f32.s32 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1944 {"inst": "vcvt.s32.f32 Dd, Dn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1945 {"inst": "vcvt.s32.f32 Vd, Vn, #fbits" , "t32": "1110|11111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1946 {"inst": "vcvt.f32.u32 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11100|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1947 {"inst": "vcvt.f32.u32 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11100|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1948 {"inst": "vcvt.u32.f32 Dd, Dn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11110|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1949 {"inst": "vcvt.u32.f32 Vd, Vn, #fbits" , "t32": "1111|11111|Vd'|imm:6|Vd|11110|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecFBitsASIMD(fbits)"}, 1950 {"inst": "vcvta.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1951 {"inst": "vcvta.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1952 {"inst": "vcvta.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1953 {"inst": "vcvta.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|00|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1954 {"inst": "vcvtm.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00110|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1955 {"inst": "vcvtm.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1956 {"inst": "vcvtm.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00111|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1957 {"inst": "vcvtm.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1958 {"inst": "vcvtm.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1959 {"inst": "vcvtm.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1960 {"inst": "vcvtm.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1961 {"inst": "vcvtm.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|11|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1962 {"inst": "vcvtn.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00010|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1963 {"inst": "vcvtn.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00010|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1964 {"inst": "vcvtn.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00011|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1965 {"inst": "vcvtn.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00011|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1966 {"inst": "vcvtn.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1967 {"inst": "vcvtn.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1968 {"inst": "vcvtn.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1969 {"inst": "vcvtn.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|01|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1970 {"inst": "vcvtp.s32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00100|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1971 {"inst": "vcvtp.s32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00100|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1972 {"inst": "vcvtp.u32.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00101|0|Vn'|0|Vn" , "ext": "ARMv8+"}, 1973 {"inst": "vcvtp.u32.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|00101|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1974 {"inst": "vcvtp.s32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10101|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1975 {"inst": "vcvtp.s32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10111|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1976 {"inst": "vcvtp.u32.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10100|1|'Vn|0|Vn" , "ext": "ARMv8+"}, 1977 {"inst": "vcvtp.u32.f64 Sd, Dn" , "t32": "1111|11101|'Vd|11|11|10|Vd|10110|1|Vn'|0|Vn" , "ext": "ARMv8+"}, 1978 {"inst": "vdup.8 Dd, Rn!=PC" , "t32": "1110|11101|1|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"}, 1979 {"inst": "vdup.8 Vd, Rn!=PC" , "t32": "1110|11101|1|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"}, 1980 {"inst": "vdup.16 Dd, Rn!=PC" , "t32": "1110|11101|0|00|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"}, 1981 {"inst": "vdup.16 Vd, Rn!=PC" , "t32": "1110|11101|0|10|Vd|Rn|1011|Vd'|0|1|1|0000" , "ext": "ASIMD"}, 1982 {"inst": "vdup.32 Dd, Rn!=PC" , "t32": "1110|11101|0|00|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"}, 1983 {"inst": "vdup.32 Vd, Rn!=PC" , "t32": "1110|11101|0|10|Vd|Rn|1011|Vd'|0|0|1|0000" , "ext": "ASIMD"}, 1984 {"inst": "vdup.8 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:3|1|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1985 {"inst": "vdup.8 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:3|1|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1986 {"inst": "vdup.16 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:2|10|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1987 {"inst": "vdup.16 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:2|10|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1988 {"inst": "vdup.32 Dd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:1|100|Vd|1100|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 1989 {"inst": "vdup.32 Vd, Dn[#i]" , "t32": "1111|11111|Vd'|11|i:1|100|Vd|1100|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 1990 {"inst": "veor.any Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1991 {"inst": "veor.any Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1992 {"inst": "vext.8 Dd, Dn, Dm, #immZ<=07" , "t32": "1110|11111|Vd'|11|Vn|Vd|immZ:4|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 1993 {"inst": "vext.8 Vd, Vn, Vm, #immZ<=15" , "t32": "1110|11111|Vd'|11|Vn|Vd|immZ:4|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 1994 {"inst": "vfma.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1995 {"inst": "vfma.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1996 {"inst": "vfma.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 1997 {"inst": "vfma.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 1998 {"inst": "vfms.f16 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 1999 {"inst": "vfms.f16 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 2000 {"inst": "vfms.f32 Dx, Dn, Dm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2001 {"inst": "vfms.f32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 2002 {"inst": "vhadd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2003 {"inst": "vhadd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2004 {"inst": "vhsub.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2005 {"inst": "vhsub.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2006 {"inst": "vins.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|0000|Vd|1010|11|'Vn|0|Vn" , "ext": "FP16"}, 2007 {"inst": "vld1.8-64 Dd, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|1111" , "ext": "ASIMD"}, 2008 {"inst": "vld1.8-64 Dd, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2009 {"inst": "vld1.8-64 Dd, [Rn!=PC, #off==8]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0111|sz|0|align:1|1101" , "ext": "ASIMD"}, 2010 {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|1111" , "ext": "ASIMD"}, 2011 {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2012 {"inst": "vld1.8-64 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1010|sz|0|align:1|1101" , "ext": "ASIMD"}, 2013 {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|1111" , "ext": "ASIMD"}, 2014 {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2015 {"inst": "vld1.8-64 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0110|sz|0|align:1|1101" , "ext": "ASIMD"}, 2016 {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|1111" , "ext": "ASIMD"}, 2017 {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2018 {"inst": "vld1.8-64 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0010|sz|0|align:1|1101" , "ext": "ASIMD"}, 2019 {"inst": "vld1.8 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|1111" , "ext": "ASIMD"}, 2020 {"inst": "vld1.8 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|Rm" , "ext": "ASIMD"}, 2021 {"inst": "vld1.8 Dd[#i], [Rn!=PC, #off==1]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0000|i:3|align:1|1101" , "ext": "ASIMD"}, 2022 {"inst": "vld1.16 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1111" , "ext": "ASIMD"}, 2023 {"inst": "vld1.16 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|Rm" , "ext": "ASIMD"}, 2024 {"inst": "vld1.16 Dd[#i], [Rn!=PC, #off==2]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0100|i:2|0|align:1|1101" , "ext": "ASIMD"}, 2025 {"inst": "vld1.32 Dd[#i], [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1111" , "ext": "ASIMD"}, 2026 {"inst": "vld1.32 Dd[#i], [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|Rm" , "ext": "ASIMD"}, 2027 {"inst": "vld1.32 Dd[#i], [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1000|i:1|0|align:2|1101" , "ext": "ASIMD"}, 2028 {"inst": "vld1r.8-32 Dd, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|1111" , "ext": "ASIMD"}, 2029 {"inst": "vld1r.8-32 Dd, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2030 {"inst": "vld1r.8-32 Dd, [Rn!=PC, #off==1<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|0|align:1|1101" , "ext": "ASIMD"}, 2031 {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|1111" , "ext": "ASIMD"}, 2032 {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|Rm" , "ext": "ASIMD"}, 2033 {"inst": "vld1r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==1<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1100|sz|1|align:1|1101" , "ext": "ASIMD"}, 2034 {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|1111" , "ext": "ASIMD"}, 2035 {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|Rm" , "ext": "ASIMD"}, 2036 {"inst": "vld2.8-32 2x{Dd<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1000|sz|align:2|1101" , "ext": "ASIMD"}, 2037 {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|1111" , "ext": "ASIMD"}, 2038 {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|Rm" , "ext": "ASIMD"}, 2039 {"inst": "vld2.8-32 2x{Dd<=29}++, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|1001|sz|align:2|1101" , "ext": "ASIMD"}, 2040 {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|1111" , "ext": "ASIMD"}, 2041 {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|Rm" , "ext": "ASIMD"}, 2042 {"inst": "vld2.8-32 4x{Dd<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0011|sz|align:2|1101" , "ext": "ASIMD"}, 2043 {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|1111" , "ext": "ASIMD"}, 2044 {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|Rm" , "ext": "ASIMD"}, 2045 {"inst": "vld2.8 2x{Dd<=30[#i]}+, [Rn!=PC, #off==2]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0001|i:3|align:1|1101" , "ext": "ASIMD"}, 2046 {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1111" , "ext": "ASIMD"}, 2047 {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|Rm" , "ext": "ASIMD"}, 2048 {"inst": "vld2.16 2x{Dd<=30[#i]}+, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|0|align:1|1101" , "ext": "ASIMD"}, 2049 {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1111" , "ext": "ASIMD"}, 2050 {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|Rm" , "ext": "ASIMD"}, 2051 {"inst": "vld2.16 2x{Dd<=29[#i]}++, [Rn!=PC, #off==4]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0101|i:2|1|align:1|1101" , "ext": "ASIMD"}, 2052 {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1111" , "ext": "ASIMD"}, 2053 {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|Rm" , "ext": "ASIMD"}, 2054 {"inst": "vld2.32 2x{Dd<=30[#i]}+, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|0|0|align:1|1101" , "ext": "ASIMD"}, 2055 {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1111" , "ext": "ASIMD"}, 2056 {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|Rm" , "ext": "ASIMD"}, 2057 {"inst": "vld2.32 2x{Dd<=29[#i]}++, [Rn!=PC, #off==8]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1001|i:1|1|0|align:1|1101" , "ext": "ASIMD"}, 2058 {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|1111" , "ext": "ASIMD"}, 2059 {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2060 {"inst": "vld2r.8-32 2x{Dd<=30}+, [Rn!=PC, #off==2<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|0|align:1|1101" , "ext": "ASIMD"}, 2061 {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|1111" , "ext": "ASIMD"}, 2062 {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|Rm" , "ext": "ASIMD"}, 2063 {"inst": "vld2r.8-32 2x{Dd<=29}++, [Rn!=PC, #off==2<<sz]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1101|sz|1|align:1|1101" , "ext": "ASIMD"}, 2064 {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|1111" , "ext": "ASIMD"}, 2065 {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2066 {"inst": "vld3.8-32 3x{Dd<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0100|sz|0|align:1|1101" , "ext": "ASIMD"}, 2067 {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|1111" , "ext": "ASIMD"}, 2068 {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|Rm" , "ext": "ASIMD"}, 2069 {"inst": "vld3.8-32 3x{Dd<=27}++, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vd'|10|Rn|Vd|0101|sz|1|align:1|1101" , "ext": "ASIMD"}, 2070 {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|1111" , "ext": "ASIMD"}, 2071 {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|Rm" , "ext": "ASIMD"}, 2072 {"inst": "vld3.8 3x{Dd<=29[#i]}+, [Rn!=PC, #off==3]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0010|i:3|0|1101" , "ext": "ASIMD"}, 2073 {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|1111" , "ext": "ASIMD"}, 2074 {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|Rm" , "ext": "ASIMD"}, 2075 {"inst": "vld3.16 3x{Dd<=29[#i]}+, [Rn!=PC, #off==6]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|00|1101" , "ext": "ASIMD"}, 2076 {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|1111" , "ext": "ASIMD"}, 2077 {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|Rm" , "ext": "ASIMD"}, 2078 {"inst": "vld3.16 3x{Dd<=27[#i]}++, [Rn!=PC, #off==6]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|0110|i:2|10|1101" , "ext": "ASIMD"}, 2079 {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC]" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|1111" , "ext": "ASIMD"}, 2080 {"inst": "vld3.32 3x{Dd<=29[#i]}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10011|Vd'|10|Rn|Vd|1010|i:1|000|Rm" , "ext": "ASIMD"}, 2081 {"inst": "vld3.32 3x{Dd<=29[#i]}+, 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"1111|11111|Vx'|10|Vn|Vx|0101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 2175 {"inst": "vmls.x16 Dx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 2176 {"inst": "vmls.x16 Vx, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vx'|01|Vn|Vx|0100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 2177 {"inst": "vmls.x32 Dx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 2178 {"inst": "vmls.x32 Vx, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vx'|10|Vn|Vx|0100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 2179 {"inst": "vmlsl.x8-32 Vx, Dn, Dm" , "t32": "111U|11111|Vx'|sz|Vn|Vx|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 2180 {"inst": "vmlsl.x16 Vx, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vx'|01|Vn|Vx|0110|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"}, 2181 {"inst": "vmlsl.x32 Vx, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vx'|10|Vn|Vx|0110|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 2182 {"inst": "vmov Rd!=PC, Sn" , "t32": "1110|11100|0|01|Vn|Rd|1010|'Vn|00|1|0000" , "ext": "ASIMD"}, 2183 {"inst": "vmov Sd, Rn!=PC" , "t32": "1110|11100|0|00|Vd|Rn|1010|'Vd|00|1|0000" , "ext": "ASIMD"}, 2184 {"inst": "vmov Rd!=PC, Rd2!=PC, Ss!=31, Ss2+" , "t32": "1110|11000|1|01|Rd2|Rd|101|000|'Vs|1|Vs" , "ext": "ASIMD"}, 2185 {"inst": "vmov Sd!=31, Sd2+, Rs!=PC, Rs2!=PC" , "t32": "1110|11000|1|00|Rs2|Rs|101|000|'Vd|1|Vd" , "ext": "ASIMD"}, 2186 {"inst": "vmov Rd!=PC, Rd2!=PC, Ds" , "t32": "1110|11000|1|01|Rd2|Rd|1011|0|0|Vs'|1|Vs" , "ext": "ASIMD"}, 2187 {"inst": "vmov Dd, Rs!=PC, Rs2!=PC" , "t32": "1110|11000|1|00|Rs2|Rs|1011|0|0|Vd'|1|Vd" , "ext": "ASIMD"}, 2188 {"inst": "vmov.x8 Dd[#i], Rn!=PC" , "t32": "1110|11100|1|i:1|0|Vd|Rn|1011|Vd'|i:2|1|0000" , "ext": "ASIMD"}, 2189 {"inst": "vmov.x16 Dd[#i], Rn!=PC" , "t32": "1110|11100|0|i:1|0|Vd|Rn|1011|Vd'|i:1|110000" , "ext": "ASIMD"}, 2190 {"inst": "vmov.x32 Dd[#i], Rn!=PC" , "t32": "1110|11100|0|i:1|0|Vd|Rn|1011|Vd'|001|0000" , "ext": "ASIMD"}, 2191 {"inst": "vmov.x8 Rd!=PC, Dn[#i]" , "t32": "1110|1110U|1|i:1|1|Vn|Rd|1011|Vn'|i:2|1|0000" , "ext": "ASIMD"}, 2192 {"inst": "vmov.x16 Rd!=PC, Dn[#i]" , "t32": "1110|1110U|0|i:1|1|Vn|Rd|1011|Vn'|i:1|110000" , "ext": "ASIMD"}, 2193 {"inst": "vmov.x32 Rd!=PC, Dn[#i]" , "t32": "1110|11100|0|i:1|1|Vn|Rd|1011|Vn'|001|0000" , "ext": "ASIMD"}, 2194 {"inst": "vmov.any Dd, Dn" , "t32": "1110|11110|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|0|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"}, 2195 {"inst": "vmov.any Vd, Vn" , "t32": "1110|11110|Vd'|10|Vn[3:0]|Vd|0001|Vn[4]|1|Vn[4]|1|Vn[3:0]", "ext": "ASIMD", "aliasOf": "vorr"}, 2196 {"inst": "vmov.x8-64 Dd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"}, 2197 {"inst": "vmov.x8-64 Vd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 0, immV)"}, 2198 {"inst": "vmovl.x8 Vd, Dn" , "t32": "111U|11111|Vd'|00|1000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"}, 2199 {"inst": "vmovl.x16 Vd, Dn" , "t32": "111U|11111|Vd'|01|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"}, 2200 {"inst": "vmovl.x32 Vd, Dn" , "t32": "111U|11111|Vd'|10|0000|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "widen"}, 2201 {"inst": "vmovn.x16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"}, 2202 {"inst": "vmul.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 2203 {"inst": "vmul.f16 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 2204 {"inst": "vmul.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2205 {"inst": "vmul.f32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 2206 {"inst": "vmul.x8-32|p8 Dd, Dn, Dm" , "t32": "111P|11110|Vd'|sz|Vn|Vd|1001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2207 {"inst": "vmul.x8-32|p8 Vd, Vn, Vm" , "t32": "111P|11110|Vd'|sz|Vn|Vd|1001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 2208 {"inst": "vmul.f32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 2209 {"inst": "vmul.f32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1001|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 2210 {"inst": "vmul.x16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 2211 {"inst": "vmul.x16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1000|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD"}, 2212 {"inst": "vmul.x32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 2213 {"inst": "vmul.x32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1000|Vn'|1|i:1|0|Vm" , "ext": "ASIMD"}, 2214 {"inst": "vmull.x8-32|p8 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 2215 {"inst": "vmull.p64 Vd, Dn, Dm" , "t32": "1110|11111|Vd'|10|Vn|Vd|11P0|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 2216 {"inst": "vmull.x16 Vd, Dn, Dm<=07[#i]" , "t32": "111U|11111|Vd'|01|Vn|Vd|1010|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "vecOp": "widen"}, 2217 {"inst": "vmull.x32 Vd, Dn, Dm<=15[#i]" , "t32": "111U|11111|Vd'|10|Vn|Vd|1010|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 2218 {"inst": "vmvn.any Dd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|00|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"}, 2219 {"inst": "vmvn.any Vd, #immV" , "t32": "111|imm:1|11111|Vd'|000|imm:3|Vd|cmode:4|01|op|1|imm:4" , "ext": "ASIMD", "imm": "VecMovImm(sz, 1, immV)"}, 2220 {"inst": "vmvn.any Dd, Dn" , "t32": "1111|11111|Vd'|11|0000|Vd|0101|10|Vn'|0|Vn" , "ext": "ASIMD"}, 2221 {"inst": "vmvn.any Vd, Vn" , "t32": "1111|11111|Vd'|11|0000|Vd|0101|11|Vn'|0|Vn" , "ext": "ASIMD"}, 2222 {"inst": "vneg.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"}, 2223 {"inst": "vneg.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"}, 2224 {"inst": "vneg.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|10|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"}, 2225 {"inst": "vneg.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0111|11|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"}, 2226 {"inst": "vneg.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0011|10|Vn'|0|Vn" , "ext": "ASIMD"}, 2227 {"inst": "vneg.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|01|Vd|0011|11|Vn'|0|Vn" , "ext": "ASIMD"}, 2228 {"inst": "vorn.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"}, 2229 {"inst": "vorn.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 1, immV)", "pseudoOf": "vorr"}, 2230 {"inst": "vorn.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2231 {"inst": "vorn.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 2232 {"inst": "vorr.x16-64 Dx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0001|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 2233 {"inst": "vorr.x16-64 Vx, #immV" , "t32": "111|imm:1|11111|Vx'|000|imm:3|Vx|cmode:4|0101|imm:4" , "ext": "ASIMD", "imm": "VecBicOrrImm(sz, 0, immV)"}, 2234 {"inst": "vorr.any Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2235 {"inst": "vorr.any Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 2236 {"inst": "vpadal.x8-32 Dx, Dn" , "t32": "1111|11111|Vx'|11|sz|00|Vx|0110|U|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2237 {"inst": "vpadal.x8-32 Vx, Vn" , "t32": "1111|11111|Vx'|11|sz|00|Vx|0110|U|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2238 {"inst": "vpadd.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"}, 2239 {"inst": "vpadd.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"}, 2240 {"inst": "vpaddl.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0010|U|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2241 {"inst": "vpaddl.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0010|U|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2242 {"inst": "vpmax.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"}, 2243 {"inst": "vpmax.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"}, 2244 {"inst": "vpmax.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2245 {"inst": "vpmin.f16 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16", "it": "out"}, 2246 {"inst": "vpmin.f32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "it": "out"}, 2247 {"inst": "vpmin.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|1010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2248 {"inst": "vpop.32 SdList" , "t32": "1110|11001|immVd[0]|11|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"}, 2249 {"inst": "vpop.64 DdList" , "t32": "1110|11001|immVd[4]|11|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"}, 2250 {"inst": "vpush.32 SdList" , "t32": "1110|11010|immVd[0]|10|1101|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"}, 2251 {"inst": "vpush.64 DdList" , "t32": "1110|11010|immVd[4]|10|1101|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"}, 2252 {"inst": "vqabs.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|0|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2253 {"inst": "vqabs.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2254 {"inst": "vqadd.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2255 {"inst": "vqadd.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2256 {"inst": "vqdmlal.s16-32 Vx, Dn, Dm" , "t32": "1110|11111|Vx'|sz|Vn|Vx|1001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2257 {"inst": "vqdmlal.s16 Vx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2258 {"inst": "vqdmlal.s32 Vx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2259 {"inst": "vqdmlsl.s16-32 Vx, Dn, Dm" , "t32": "1110|11111|Vx'|sz|Vn|Vx|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2260 {"inst": "vqdmlsl.s16 Vx, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vx'|01|Vn|Vx|0111|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2261 {"inst": "vqdmlsl.s32 Vx, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vx'|10|Vn|Vx|0111|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2262 {"inst": "vqdmulh.s16-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2263 {"inst": "vqdmulh.s16-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2264 {"inst": "vqdmulh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2265 {"inst": "vqdmulh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1100|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2266 {"inst": "vqdmulh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2267 {"inst": "vqdmulh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1100|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2268 {"inst": "vqdmull.s16-32 Vd, Dn, Dm" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2269 {"inst": "vqdmull.s16 Vd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1011|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2270 {"inst": "vqdmull.s32 Vd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1011|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "widen"}, 2271 {"inst": "vqmovn.x16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1|U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 2272 {"inst": "vqmovun.s16-64 Dd, Vn" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|0|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 2273 {"inst": "vqneg.s8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|1|0|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2274 {"inst": "vqneg.s8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0111|1|1|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2275 {"inst": "vqrdmulh.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2276 {"inst": "vqrdmulh.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2277 {"inst": "vqrdmulh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2278 {"inst": "vqrdmulh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|01|Vn|Vd|1101|Vn'|1|i:1|0|i:1|Vm:3" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2279 {"inst": "vqrdmulh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2280 {"inst": "vqrdmulh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2281 {"inst": "vqrshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2282 {"inst": "vqrshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2283 {"inst": "vqrshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 2284 {"inst": "vqrshrn.x16-64 Dd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|1001|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 2285 {"inst": "vqrshrun.s16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 2286 {"inst": "vqrshrun.s16-64 Dd, Vn, #n" , "t32": "1111|11111|Vd'|imm:6|Vd|1000|01|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 2287 {"inst": "vqshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2288 {"inst": "vqshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2289 {"inst": "vqshl.x8-64 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0111|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 2290 {"inst": "vqshl.x8-64 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0111|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 2291 {"inst": "vqshlu.s8-64 Dd, Dn, #n" , "t32": "1111|11111|Vd'|imm[5:0]|Vd|0110|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 2292 {"inst": "vqshlu.s8-64 Vd, Vn, #n" , "t32": "1111|11111|Vd'|imm[5:0]|Vd|0110|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftPImm(sz, n)"}, 2293 {"inst": "vqshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|1U|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 2294 {"inst": "vqshrn.x16-64 Dd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|1001|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 2295 {"inst": "vqshrun.s16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|szM1:2|10|Vd|0010|01|Vn'|0|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "vecOp": "narrow"}, 2296 {"inst": "vqshrun.s16-64 Dd, Vn, #n" , "t32": "1111|11111|Vd'|imm:6|Vd|1000|0|0|Vn'|1|Vn" , "ext": "ASIMD", "fpcsr": "Q=X", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 2297 {"inst": "vqsub.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2298 {"inst": "vqsub.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0010|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "fpcsr": "Q=X"}, 2299 {"inst": "vraddhn.x16-64 Dd, Vn, Vm" , "t32": "1111|11111|Vd'|szM1:2|Vn|Vd|0100|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 2300 {"inst": "vrecpe.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 2301 {"inst": "vrecpe.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD FP16"}, 2302 {"inst": "vrecpe.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0101|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2303 {"inst": "vrecpe.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0101|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2304 {"inst": "vrecpe.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0100|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2305 {"inst": "vrecpe.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|0100|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2306 {"inst": "vrecps.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 2307 {"inst": "vrecps.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|01|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16"}, 2308 {"inst": "vrecps.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2309 {"inst": "vrecps.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|00|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 2310 {"inst": "vrev16.x8 Dd, Dn" , "t32": "1111|11111|Vd'|11|00|00|Vd|0001|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2311 {"inst": "vrev16.x8 Vd, Vn" , "t32": "1111|11111|Vd'|11|00|00|Vd|0001|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2312 {"inst": "vrev32.x8-16 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|1|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2313 {"inst": "vrev32.x8-16 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|1|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2314 {"inst": "vrev64.x8-32 Dd, Dn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|0|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2315 {"inst": "vrev64.x8-32 Vd, Vn" , "t32": "1111|11111|Vd'|11|sz|00|Vd|0000|0|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2316 {"inst": "vrhadd.x8-32 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0001|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2317 {"inst": "vrhadd.x8-32 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vn|Vd|0001|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2318 {"inst": "vrinta.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|00|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2319 {"inst": "vrinta.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|00|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2320 {"inst": "vrinta.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|00|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 2321 {"inst": "vrinta.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2322 {"inst": "vrinta.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16"}, 2323 {"inst": "vrinta.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|00|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2324 {"inst": "vrinta.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 2325 {"inst": "vrintm.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2326 {"inst": "vrintm.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2327 {"inst": "vrintm.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 2328 {"inst": "vrintm.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2329 {"inst": "vrintm.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2330 {"inst": "vrintm.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|10|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2331 {"inst": "vrintm.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|10|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2332 {"inst": "vrintn.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|01|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2333 {"inst": "vrintn.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|01|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2334 {"inst": "vrintn.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|01|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 2335 {"inst": "vrintn.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2336 {"inst": "vrintn.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2337 {"inst": "vrintn.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|00|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2338 {"inst": "vrintn.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|01|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2339 {"inst": "vrintp.f16 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2340 {"inst": "vrintp.f32 Sd, Sn" , "t32": "1111|11101|'Vd|11|10|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2341 {"inst": "vrintp.f64 Dd, Dn" , "t32": "1111|11101|Vd'|11|10|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 2342 {"inst": "vrintp.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2343 {"inst": "vrintp.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2344 {"inst": "vrintp.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|11|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2345 {"inst": "vrintp.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|11|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2346 {"inst": "vrintr.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2347 {"inst": "vrintr.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2348 {"inst": "vrintr.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|10|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 2349 {"inst": "vrintx.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10|01|01|'Vn|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2350 {"inst": "vrintx.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|11|Vd|10|10|01|'Vn|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2351 {"inst": "vrintx.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|11|Vd|10|11|01|Vn'|0|Vn" , "ext": "ARMv8+"}, 2352 {"inst": "vrintx.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2353 {"inst": "vrintx.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2354 {"inst": "vrintx.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2355 {"inst": "vrintx.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|00|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2356 {"inst": "vrintz.f16 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|01|11|'Vn|0|Vn" , "ext": "ARMv8+ FP16"}, 2357 {"inst": "vrintz.f32 Sd, Sn" , "t32": "1110|11101|'Vd|11|01|10|Vd|10|10|11|'Vn|0|Vn" , "ext": "ARMv8+"}, 2358 {"inst": "vrintz.f64 Dd, Dn" , "t32": "1110|11101|Vd'|11|01|10|Vd|10|11|11|Vn'|0|Vn" , "ext": "ARMv8+"}, 2359 {"inst": "vrintz.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2360 {"inst": "vrintz.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+ FP16", "it": "out"}, 2361 {"inst": "vrintz.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|10|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2362 {"inst": "vrintz.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|10|Vd|01|01|11|Vn'|0|Vn" , "ext": "ARMv8+", "it": "out"}, 2363 {"inst": "vrshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2364 {"inst": "vrshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0101|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2365 {"inst": "vrshr.x8-32 Dd, Dn, #zero" , "t32": "1110|11110|Vd'|10|Vd|Vd|0001|Vn'|0|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"}, 2366 {"inst": "vrshr.x8-32 Vd, Vn, #zero" , "t32": "1110|11110|Vd'|10|Vd|Vd|0001|Vn'|1|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"}, 2367 {"inst": "vrshr.x8-32 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|0010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2368 {"inst": "vrshr.x8-32 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm:6|Vd|0010|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2369 {"inst": "vrshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|1|Vn" , "ext": "ASIMD", "vecOp": "narrow", "pseudoOf": "vmovn"}, 2370 {"inst": "vrshrn.x16-64 Dd, Vn, #n" , "t32": "1110|11111|Vd'|imm:6|Vd|1000|0|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 2371 {"inst": "vrsqrte.f16 Dd, Dn" , "t32": "1111|11111|Vd'|11|01|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"}, 2372 {"inst": "vrsqrte.f16 Vd, Vn" , "t32": "1111|11111|Vd'|11|01|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD FP16", "it": "out"}, 2373 {"inst": "vrsqrte.f32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|01|10|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"}, 2374 {"inst": "vrsqrte.f32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|01|11|Vn'|0|Vn" , "ext": "ASIMD", "it": "out"}, 2375 {"inst": "vrsqrte.u32 Dd, Dn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|00|10|Vn'|0|Vn" , "ext": "ASIMD"}, 2376 {"inst": "vrsqrte.u32 Vd, Vn" , "t32": "1111|11111|Vd'|11|10|11|Vd|01|00|11|Vn'|0|Vn" , "ext": "ASIMD"}, 2377 {"inst": "vrsqrts.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"}, 2378 {"inst": "vrsqrts.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD FP16", "it": "out"}, 2379 {"inst": "vrsqrts.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"}, 2380 {"inst": "vrsqrts.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|1111|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD", "it": "out"}, 2381 {"inst": "vrsra.x8-64 Dx, Dn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0011|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2382 {"inst": "vrsra.x8-64 Vx, Vn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0011|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2383 {"inst": "vrsubhn.x16-64 Dd, Vn, Vm" , "t32": "1111|11111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 2384 {"inst": "vseleq.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|00|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"}, 2385 {"inst": "vseleq.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|00|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2386 {"inst": "vseleq.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|00|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2387 {"inst": "vselge.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|10|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"}, 2388 {"inst": "vselge.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|10|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2389 {"inst": "vselge.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|10|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2390 {"inst": "vselgt.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|11|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"}, 2391 {"inst": "vselgt.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|11|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2392 {"inst": "vselgt.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2393 {"inst": "vselvs.f16 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|01|Vn|Vd|10|01|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+ FP16", "it": "out"}, 2394 {"inst": "vselvs.f32 Sd, Sn, Sm" , "t32": "1111|11100|'Vd|01|Vn|Vd|10|10|'Vn|0|'Vm|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2395 {"inst": "vselvs.f64 Dd, Dn, Dm" , "t32": "1111|11100|Vd'|01|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ARMv8+", "it": "out"}, 2396 {"inst": "vshl.x8-64 Dd, Dn, Dm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|0|Vn'|0|Vn" , "ext": "ASIMD"}, 2397 {"inst": "vshl.x8-64 Vd, Vn, Vm" , "t32": "111U|11110|Vd'|sz|Vm|Vd|0100|Vm'|1|Vn'|0|Vn" , "ext": "ASIMD"}, 2398 {"inst": "vshl.x8-64 Dd, Dn, #n" , "t32": "1110|11111|Vd'|imm[5:0]|Vd|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 2399 {"inst": "vshl.x8-64 Vd, Vn, #n" , "t32": "1110|11111|Vd'|imm[5:0]|Vd|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 2400 {"inst": "vshll.x8-32 Vd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|1010|0|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)", "vecOp": "widen"}, 2401 {"inst": "vshr.x8-64 Dd, Dn, #zero" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|0|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"}, 2402 {"inst": "vshr.x8-64 Vd, Vn, #zero" , "t32": "1110|11110|Vd'|10|Vn|Vd|0001|Vn'|1|Vn'|1|Vn" , "ext": "ASIMD", "pseudoOf": "vorr"}, 2403 {"inst": "vshr.x8-64 Dd, Dn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0000|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2404 {"inst": "vshr.x8-64 Vd, Vn, #n" , "t32": "111U|11111|Vd'|imm[5:0]|Vd|0000|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2405 {"inst": "vshrn.x16-64 Dd, Vn, #zero" , "t32": "1111|11111|Vd'|11|sz|10|Vd|0010|00|Vn'|0|Vn" , "ext": "ASIMD", "vecOp": "narrow"}, 2406 {"inst": "vshrn.x16-64 Dd, Vn, #n" , "t32": "1110|11111|Vd'|imm:6|Vd|1000|00|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNarrowImm(sz, n)", "vecOp": "narrow"}, 2407 {"inst": "vsli.x8-64 Dx, Dn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0101|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 2408 {"inst": "vsli.x8-64 Vx, Vn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0101|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftPImm(sz, n)"}, 2409 {"inst": "vsra.x8-64 Dx, Dn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0001|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2410 {"inst": "vsra.x8-64 Vx, Vn, #n" , "t32": "111U|11111|Vx'|imm[5:0]|Vx|0001|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2411 {"inst": "vsri.x8-64 Dx, Dn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0100|imm[6]|0|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2412 {"inst": "vsri.x8-64 Vx, Vn, #n" , "t32": "1111|11111|Vx'|imm[5:0]|Vx|0100|imm[6]|1|Vn'|1|Vn" , "ext": "ASIMD", "imm": "VecShiftNImm(sz, n)"}, 2413 {"inst": "vst1.8-64 Ds, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|1111" , "ext": "ASIMD"}, 2414 {"inst": "vst1.8-64 Ds, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2415 {"inst": "vst1.8-64 Ds, [Rn!=PC, #off==8]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0111|sz|0|align:1|1101" , "ext": "ASIMD"}, 2416 {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|1111" , "ext": "ASIMD"}, 2417 {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2418 {"inst": "vst1.8-64 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1010|sz|0|align:1|1101" , "ext": "ASIMD"}, 2419 {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|1111" , "ext": "ASIMD"}, 2420 {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2421 {"inst": "vst1.8-64 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0110|sz|0|align:1|1101" , "ext": "ASIMD"}, 2422 {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|1111" , "ext": "ASIMD"}, 2423 {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2424 {"inst": "vst1.8-64 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0010|sz|0|align:1|1101" , "ext": "ASIMD"}, 2425 {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|1111" , "ext": "ASIMD"}, 2426 {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|Rm" , "ext": "ASIMD"}, 2427 {"inst": "vst2.8-32 2x{Ds<=30}+, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1000|sz|align:2|1101" , "ext": "ASIMD"}, 2428 {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|1111" , "ext": "ASIMD"}, 2429 {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|Rm" , "ext": "ASIMD"}, 2430 {"inst": "vst2.8-32 2x{Ds<=29}++, [Rn!=PC, #off==16]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|1001|sz|align:2|1101" , "ext": "ASIMD"}, 2431 {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|1111" , "ext": "ASIMD"}, 2432 {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|Rm" , "ext": "ASIMD"}, 2433 {"inst": "vst2.8-32 4x{Ds<=28}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0011|sz|align:2|1101" , "ext": "ASIMD"}, 2434 {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|1111" , "ext": "ASIMD"}, 2435 {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|Rm" , "ext": "ASIMD"}, 2436 {"inst": "vst3.8-32 3x{Ds<=29}+, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0100|sz|0|align:1|1101" , "ext": "ASIMD"}, 2437 {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|1111" , "ext": "ASIMD"}, 2438 {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|Rm" , "ext": "ASIMD"}, 2439 {"inst": "vst3.8-32 3x{Ds<=27}++, [Rn!=PC, #off==24]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0101|sz|1|align:1|1101" , "ext": "ASIMD"}, 2440 {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|1111" , "ext": "ASIMD"}, 2441 {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|Rm" , "ext": "ASIMD"}, 2442 {"inst": "vst4.8-32 4x{Ds<=29}+, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0000|sz|align:2|1101" , "ext": "ASIMD"}, 2443 {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC]" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|1111" , "ext": "ASIMD"}, 2444 {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, Rm!=XX]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|Rm" , "ext": "ASIMD"}, 2445 {"inst": "vst4.8-32 4x{Ds<=27}++, [Rn!=PC, #off==32]@" , "t32": "1111|10010|Vs'|00|Rn|Vs|0001|sz|align:2|1101" , "ext": "ASIMD"}, 2446 {"inst": "vstmdb.32 [Rn!=PC]!, SdList" , "t32": "1110|11010|immVd[0]|10|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"}, 2447 {"inst": "vstmdb.64 [Rn!=PC]!, DdList" , "t32": "1110|11010|immVd[4]|10|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"}, 2448 {"inst": "vstmia.32 [Rn!=PC]{!}, SdList" , "t32": "1110|11001|immVd[0]|W0|Rn|immVd[4:1]|1010|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecSListImm(SdList)"}, 2449 {"inst": "vstmia.64 [Rn!=PC]{!}, DdList" , "t32": "1110|11001|immVd[4]|W0|Rn|immVd[3:0]|1011|immCount:8" , "ext": "ASIMD", "it": "any", "imm": "VecDListImm(SdList)"}, 2450 {"inst": "vsub.f16 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|11|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 2451 {"inst": "vsub.f16 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|11|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD FP16"}, 2452 {"inst": "vsub.f32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|10|Vn|Vd|11|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2453 {"inst": "vsub.f32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|10|Vn|Vd|11|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2454 {"inst": "vsub.x8-64 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2455 {"inst": "vsub.x8-64 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2456 {"inst": "vsubhn.x16-64 Dd, Vn, Vm" , "t32": "1110|11111|Vd'|szM1:2|Vn|Vd|0110|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "narrow"}, 2457 {"inst": "vsubl.x8-32 Vd, Dn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0010|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 2458 {"inst": "vsubw.x8-32 Vd, Vn, Dm" , "t32": "111U|11111|Vd'|sz|Vn|Vd|0011|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD", "vecOp": "widen"}, 2459 {"inst": "vswp.any Dx, Dx2!=Dx" , "t32": "1111|11111|Vx'|11|00|10|Vx|0000|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 2460 {"inst": "vswp.any Vx, Vx2!=Vx" , "t32": "1111|11111|Vx'|11|00|10|Vx|0000|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"}, 2461 {"inst": "vtbl.x8 Dd, Dn, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|00|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2462 {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|01|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2463 {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|10|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2464 {"inst": "vtbl.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|11|Vn'|0|Vm'|0|Vm" , "ext": "ASIMD"}, 2465 {"inst": "vtbx.x8 Dd, Dn, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|00|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2466 {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|01|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2467 {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|10|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2468 {"inst": "vtbx.x8 Dd, Dn, Dn2+, Dn3+, Dn4+, Dm" , "t32": "1111|11111|Vd'|11|Vn|Vd|10|11|Vn'|1|Vm'|0|Vm" , "ext": "ASIMD"}, 2469 {"inst": "vtrn.x8-32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 2470 {"inst": "vtrn.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"}, 2471 {"inst": "vtst.x8-32 Dd, Dn, Dm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "ext": "ASIMD"}, 2472 {"inst": "vtst.x8-32 Vd, Vn, Vm" , "t32": "1110|11110|Vd'|sz|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "ext": "ASIMD"}, 2473 {"inst": "vuzp.x8-16 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|0|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 2474 {"inst": "vuzp.x32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"}, 2475 {"inst": "vuzp.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|0|1|Vx2'|0|Vx2" , "ext": "ASIMD"}, 2476 {"inst": "vzip.x8-16 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|1|0|Vx2'|0|Vx2" , "ext": "ASIMD"}, 2477 {"inst": "vzip.x32 Dx, Dx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0000|1|0|Vx2'|0|Vx2" , "ext": "ASIMD", "aliasOf": "vtrn"}, 2478 {"inst": "vzip.x8-32 Vx, Vx2" , "t32": "1111|11111|Vx'|11|sz|10|Vx|0001|1|1|Vx2'|0|Vx2" , "ext": "ASIMD"} 2479 ]}, 2480 2481 {"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [ 2482 {"inst": "aesd.x8 Vx, Vm" , "a32": "1111|00111|Vx'|11|00|00|Vx|0|0110|1|Vm'|0|Vm"}, 2483 {"inst": "aese.x8 Vx, Vm" , "a32": "1111|00111|Vx'|11|00|00|Vx|0|0110|0|Vm'|0|Vm"}, 2484 {"inst": "aesimc.x8 Vd, Vm" , "a32": "1111|00111|Vd'|11|00|00|Vd|0|0111|1|Vm'|0|Vm"}, 2485 {"inst": "aesmc.x8 Vd, Vm" , "a32": "1111|00111|Vd'|11|00|00|Vd|0|0111|0|Vm'|0|Vm"} 2486 ]}, 2487 2488 {"category": "ASIMD CRYPTO_HASH", "ext": "AES", "data": [ 2489 {"inst": "aesd.x8 Vx, Vm" , "t32": "1111|11111|Vx'|11|00|00|Vx|0|0110|1|Vm'|0|Vm" , "it": "out"}, 2490 {"inst": "aese.x8 Vx, Vm" , "t32": "1111|11111|Vx'|11|00|00|Vx|0|0110|0|Vm'|0|Vm" , "it": "out"}, 2491 {"inst": "aesimc.x8 Vd, Vm" , "t32": "1111|11111|Vd'|11|00|00|Vd|0|0111|1|Vm'|0|Vm" , "it": "out"}, 2492 {"inst": "aesmc.x8 Vd, Vm" , "t32": "1111|11111|Vd'|11|00|00|Vd|0|0111|0|Vm'|0|Vm" , "it": "out"} 2493 ]}, 2494 2495 {"category": "ASIMD", "ext": "BF16", "data": [ 2496 {"inst": "vmmla.bf16 Vd, Vn, Vm" , "a32": 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"1111|11100|Vd'|11|Vn|Vd|1000|Vn'|1|i:1|1|i:1|Vm[2:0]"} 2507 ]}, 2508 2509 {"category": "ASIMD", "ext": "BF16", "data": [ 2510 {"inst": "vmmla.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|00|Vn|Vd|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2511 {"inst": "vcvtb.bf16.f32 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10010|1|'Vn|0|Vn" , "it": "any"}, 2512 {"inst": "vcvtt.bf16.f32 Sd, Dn" , "t32": "1110|11101|'Vd|11|00|11|Vd|10011|1|'Vn|0|Vn" , "it": "any"}, 2513 {"inst": "vdot.bf16 Dd, Dn, Dm" , "t32": "1110|11000|Vd'|00|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"}, 2514 {"inst": "vdot.bf16 Vd, Vn, Vm" , "t32": "1110|11000|Vd'|00|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2515 {"inst": "vdot.bf16 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11100|Vd'|00|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"}, 2516 {"inst": "vdot.bf16 Vd, Vn, Dm<=15[#i]" , "t32": "1110|11100|Vd'|00|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"}, 2517 {"inst": "vfmab.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|0|Vm'|1|Vm" , "it": "out"}, 2518 {"inst": "vfmab.bf16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|0|i:1|1|i:1|Vm[2:0]" , "it": "out"}, 2519 {"inst": "vfmat.bf16 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|11|Vn|Vd|1000|Vn'|1|Vm'|1|Vm" , "it": "out"}, 2520 {"inst": "vfmat.bf16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11100|Vd'|11|Vn|Vd|1000|Vn'|1|i:1|1|i:1|Vm[2:0]" , "it": "out"} 2521 ]}, 2522 2523 {"category": "ASIMD", "ext": "DOTPROD", "data": [ 2524 {"inst": "vsdot.s8 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm"}, 2525 {"inst": "vsdot.s8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm"}, 2526 {"inst": "vsdot.s8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|0|Vm"}, 2527 {"inst": "vsdot.s8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm"}, 2528 {"inst": "vudot.u8 Dd, Dn, Dm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|1|Vm"}, 2529 {"inst": "vudot.u8 Vd, Vn, Vm" , "a32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|1|Vm"}, 2530 {"inst": "vudot.u8 Dd, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|1|Vm"}, 2531 {"inst": "vudot.u8 Vd, Vn, Dm<=15[#i]" , "a32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|1|Vm"} 2532 ]}, 2533 2534 {"category": "ASIMD", "ext": "DOTPROD", "data": [ 2535 {"inst": "vsdot.s8 Dd, Dn, Dm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|0|Vm" , "it": "out"}, 2536 {"inst": "vsdot.s8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2537 {"inst": "vsdot.s8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|0|Vm" , "it": "out"}, 2538 {"inst": "vsdot.s8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|0|Vm" , "it": "out"}, 2539 {"inst": "vudot.u8 Dd, Dn, Dm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|0|Vm'|1|Vm" , "it": "out"}, 2540 {"inst": "vudot.u8 Vd, Vn, Vm" , "t32": "1111|11000|Vd'|10|Vn|Vd|1101|Vn'|1|Vm'|1|Vm" , "it": "out"}, 2541 {"inst": "vudot.u8 Dd, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|0|i:1|1|Vm" , "it": "out"}, 2542 {"inst": "vudot.u8 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11100|Vd'|10|Vn|Vd|1101|Vn'|1|i:1|1|Vm" , "it": "out"} 2543 ]}, 2544 2545 {"category": "ASIMD", "ext": "FCMA", "data": [ 2546 {"inst": "vcadd.f32 Dd, Dn, Dm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"}, 2547 {"inst": "vcadd.f32 Vd, Vn, Vm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"}, 2548 {"inst": "vcmla.f32 Dx, Dn, Dm, #rot2" , "a32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"}, 2549 {"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "a32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"}, 2550 {"inst": "vcmla.f32 Dx, Dn, Dm[#i], #rot2" , "a32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"}, 2551 {"inst": "vcmla.f32 Vx, Vn, Dm[#i], #rot2" , "a32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"} 2552 ]}, 2553 2554 {"category": "ASIMD", "ext": "FCMA", "data": [ 2555 {"inst": "vcadd.f32 Dd, Dn, Dm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"}, 2556 {"inst": "vcadd.f32 Vd, Vn, Vm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|01|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"}, 2557 {"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "t32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}, 2558 {"inst": "vcmla.f32 Vx, Vn, Vm, #rot2" , "t32": "1111|110|imm:2|Vx'|11|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}, 2559 {"inst": "vcmla.f32 Dx, Dn, Dm[#i], #rot2" , "t32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}, 2560 {"inst": "vcmla.f32 Vx, Vn, Dm[#i], #rot2" , "t32": "1111|1110|1|Vx'|imm:2|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"} 2561 ]}, 2562 2563 {"category": "ASIMD", "ext": "FCMA FP16", "data": [ 2564 {"inst": "vcadd.f16 Dd, Dn, Dm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"}, 2565 {"inst": "vcadd.f16 Vd, Vn, Vm, #rot1" , "a32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot1Imm(rot1)"}, 2566 {"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "a32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"}, 2567 {"inst": "vcmla.f16 Vx, Vn, Vm, #rot2" , "a32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|0|Vm" , "imm": "VecRot2Imm(rot2)"}, 2568 {"inst": "vcmla.f16 Dx, Dn, Dm<=15[#i], #rot2" , "a32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|0|i:1|0|Vm" , "imm": "VecRot2Imm(rot2)"}, 2569 {"inst": "vcmla.f16 Vx, Vn, Dm<=15[#i], #rot2" , "a32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|1|i:1|0|Vm" , "imm": "VecRot2Imm(rot2)"} 2570 ]}, 2571 2572 {"category": "ASIMD", "ext": "FCMA FP16", "data": [ 2573 {"inst": "vcadd.f16 Dd, Dn, Dm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"}, 2574 {"inst": "vcadd.f16 Vd, Vn, Vm, #rot1" , "t32": "1111|110|imm:1|1|Vd'|00|Vn|Vd|1000|Vn'|1|Vm'|0|Vm" , "it": "out", "imm": "VecRot1Imm(rot1)"}, 2575 {"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "t32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}, 2576 {"inst": "vcmla.f16 Dx, Dn, Dm, #rot2" , "t32": "1111|110|imm:2|Vx'|10|Vn|Vx|1000|Vn'|0|Vm'|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}, 2577 {"inst": "vcmla.f16 Dx, Dn, Dm<=15[#i], #rot2" , "t32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|0|i:1|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"}, 2578 {"inst": "vcmla.f16 Vx, Vn, Dm<=15[#i], #rot2" , "t32": "1111|1110|0|Vx'|imm:2|Vn|Vx|1000|Vn'|1|i:1|0|Vm" , "it": "out", "imm": "VecRot2Imm(rot2)"} 2579 ]}, 2580 2581 {"category": "ASIMD", "ext": "FHM", "data": [ 2582 {"inst": "vfmal.f16 Dx, Sn, Sm" , "a32": "1111|11000|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm"}, 2583 {"inst": "vfmal.f16 Vx, Dn, Dm" , "a32": "1111|11000|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm"}, 2584 {"inst": "vfmal.f16 Dx, Sn, Sm<=15[#i]" , "a32": "1111|11100|Vx'|00|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]"}, 2585 {"inst": "vfmal.f16 Vx, Dn, Dm<=15[#i]" , "a32": "1111|11100|Vx'|00|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3"}, 2586 {"inst": "vfmsl.f16 Dx, Sn, Sm" , "a32": "1111|11001|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm"}, 2587 {"inst": "vfmsl.f16 Vx, Dn, Dm" , "a32": "1111|11001|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm"}, 2588 {"inst": "vfmsl.f16 Dx, Sn, Sm<=15[#i]" , "a32": "1111|11100|Vx'|01|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]"}, 2589 {"inst": "vfmsl.f16 Vx, Dn, Dm<=07[#i]" , "a32": "1111|11100|Vx'|01|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3"} 2590 ]}, 2591 2592 {"category": "ASIMD", "ext": "FHM", "data": [ 2593 {"inst": "vfmal.f16 Dx, Sn, Sm" , "t32": "1111|11000|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm" , "it": "out"}, 2594 {"inst": "vfmal.f16 Vx, Dn, Dm" , "t32": "1111|11000|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm" , "it": "out"}, 2595 {"inst": "vfmal.f16 Dx, Sn, Sm<=15[#i]" , "t32": "1111|11100|Vx'|00|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]" , "it": "out"}, 2596 {"inst": "vfmal.f16 Vx, Dn, Dm<=15[#i]" , "t32": "1111|11100|Vx'|00|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3" , "it": "out"}, 2597 {"inst": "vfmsl.f16 Dx, Sn, Sm" , "t32": "1111|11001|Vx'|10|Vn|Vx|1000|'Vn|0|'Vm|1|Vm" , "it": "out"}, 2598 {"inst": "vfmsl.f16 Vx, Dn, Dm" , "t32": "1111|11001|Vx'|10|Vn|Vx|1000|Vn'|1|Vm'|1|Vm" , "it": "out"}, 2599 {"inst": "vfmsl.f16 Dx, Sn, Sm<=15[#i]" , "t32": "1111|11100|Vx'|01|Vn|Vx|1000|'Vn|0|Vm[0]|1|i:1|Vm[3:1]" , "it": "out"}, 2600 {"inst": "vfmsl.f16 Vx, Dn, Dm<=07[#i]" , "t32": "1111|11100|Vx'|01|Vn|Vx|1000|Vn'|1|i:1|1|i:1|Vm:3" , "it": "out"} 2601 ]}, 2602 2603 {"category": "ASIMD", "ext": "FP16CONV", "data": [ 2604 {"inst": "vcvt.f16.f32 Dd, Vn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01100|0|Vn'|0|Vn"}, 2605 {"inst": "vcvt.f32.f16 Vd, Dn" , "a32": "1111|00111|Vd'|11|01|10|Vd|01110|0|Vn'|0|Vn"}, 2606 {"inst": "vcvt.f16.s16 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2607 {"inst": "vcvt.f16.s16 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2608 {"inst": "vcvt.s16.f16 Dd, Dn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2609 {"inst": "vcvt.s16.f16 Vd, Vn, #fbits" , "a32": "1111|00101|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2610 {"inst": "vcvt.f16.u16 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11000|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2611 {"inst": "vcvt.f16.u16 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11000|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2612 {"inst": "vcvt.u16.f16 Dd, Dn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11010|0|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2613 {"inst": "vcvt.u16.f16 Vd, Vn, #fbits" , "a32": "1111|00111|Vd'|imm:6|Vd|11010|1|Vn'|1|Vn" , "imm": "VecFBitsASIMD(fbits)"}, 2614 {"inst": "vcvta.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10011|1|'Vn|0|Vn"}, 2615 {"inst": "vcvta.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn"}, 2616 {"inst": "vcvtb.f32.f16 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|10|Vd|10100|1|'Vn|0|Vn"}, 2617 {"inst": "vcvtb.f16.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10100|1|'Vn|0|Vn"}, 2618 {"inst": "vcvtb.f64.f16 Dd, Sn" , "a32": "cond|11101|Vd'|11|00|10|Vd|10110|1|'Vn|0|Vn"}, 2619 {"inst": "vcvtb.f16.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10110|1|Vn'|0|Vn"}, 2620 {"inst": "vcvtm.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00110|0|Vn'|0|Vn"}, 2621 {"inst": "vcvtm.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00110|1|Vn'|0|Vn"}, 2622 {"inst": "vcvtm.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00111|0|Vn'|0|Vn"}, 2623 {"inst": "vcvtm.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00111|1|Vn'|0|Vn"}, 2624 {"inst": "vcvtm.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10011|1|'Vn|0|Vn"}, 2625 {"inst": "vcvtm.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|11|Vd|10010|1|'Vn|0|Vn"}, 2626 {"inst": "vcvtn.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00010|0|Vn'|0|Vn"}, 2627 {"inst": "vcvtn.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00010|1|Vn'|0|Vn"}, 2628 {"inst": "vcvtn.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00011|0|Vn'|0|Vn"}, 2629 {"inst": "vcvtn.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00011|1|Vn'|0|Vn"}, 2630 {"inst": "vcvtn.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10011|1|'Vn|0|Vn"}, 2631 {"inst": "vcvtn.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn"}, 2632 {"inst": "vcvtp.s16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00100|0|Vn'|0|Vn"}, 2633 {"inst": "vcvtp.s16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00100|1|Vn'|0|Vn"}, 2634 {"inst": "vcvtp.u16.f16 Dd, Dn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00101|0|Vn'|0|Vn"}, 2635 {"inst": "vcvtp.u16.f16 Vd, Vn" , "a32": "1111|00111|Vd'|11|01|11|Vd|00101|1|Vn'|0|Vn"}, 2636 {"inst": "vcvtp.s32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10011|1|'Vn|0|Vn"}, 2637 {"inst": "vcvtp.u32.f16 Sd, Sn" , "a32": "1111|11101|'Vd|11|11|10|Vd|10010|1|'Vn|0|Vn"}, 2638 {"inst": "vcvtr.s32.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|11|01|Vd|10010|1|'Vn|0|Vn"}, 2639 {"inst": "vcvtr.u32.f16 Sd, Sn" , "a32": "1110|11101|'Vd|11|11|00|Vd|10010|1|'Vn|0|Vn"}, 2640 {"inst": "vcvtt.f32.f16 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|10|Vd|10101|1|'Vn|0|Vn"}, 2641 {"inst": "vcvtt.f16.f32 Sd, Sn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10101|1|'Vn|0|Vn"}, 2642 {"inst": "vcvtt.f64.f16 Dd, Sn" , "a32": "cond|11101|Vd'|11|00|10|Vd|10111|1|'Vn|0|Vn"}, 2643 {"inst": "vcvtt.f16.f64 Sd, Dn" , "a32": "cond|11101|'Vd|11|00|11|Vd|10111|1|Vn'|0|Vn"} 2644 ]}, 2645 2646 {"category": "ASIMD", "ext": "FP16CONV", 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"1110|11101|'Vd|11|1001|Vd|1011|11|Vn'|0|Vn" , "it": "out"} 2719 ]}, 2720 2721 {"category": "ASIMD", "ext": "RDM", "data": [ 2722 {"inst": "vqrdmlah.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|1|Vm"}, 2723 {"inst": "vqrdmlah.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|1|Vm"}, 2724 {"inst": "vqrdmlah.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3"}, 2725 {"inst": "vqrdmlah.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3"}, 2726 {"inst": "vqrdmlah.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm"}, 2727 {"inst": "vqrdmlah.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm"}, 2728 {"inst": "vqrdmlsh.s16-32 Dd, Dn, Dm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1100|Vn'|0|Vm'|1|Vm"}, 2729 {"inst": "vqrdmlsh.s16-32 Vd, Vn, Vm" , "a32": "1111|00110|Vd'|sz|Vn|Vd|1100|Vn'|1|Vm'|1|Vm"}, 2730 {"inst": "vqrdmlsh.s16 Dd, Dn, Dm<=07[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3"}, 2731 {"inst": "vqrdmlsh.s16 Vd, Vn, Dm<=07[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3"}, 2732 {"inst": "vqrdmlsh.s32 Dd, Dn, Dm<=15[#i]" , "a32": "1111|00101|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm"}, 2733 {"inst": "vqrdmlsh.s32 Vd, Vn, Dm<=15[#i]" , "a32": "1111|00111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm"} 2734 ]}, 2735 2736 {"category": "ASIMD", "ext": "RDM", "data": [ 2737 {"inst": "vqrdmlah.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|0|Vm'|1|Vm" , "it": "out"}, 2738 {"inst": "vqrdmlah.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1011|Vn'|1|Vm'|1|Vm" , "it": "out"}, 2739 {"inst": "vqrdmlah.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"}, 2740 {"inst": "vqrdmlah.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"}, 2741 {"inst": "vqrdmlah.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm" , "it": "out"}, 2742 {"inst": "vqrdmlah.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1110|Vn'|1|i:1|0|Vm" , "it": "out"}, 2743 {"inst": "vqrdmlsh.s16-32 Dd, Dn, Dm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1100|Vn'|0|Vm'|1|Vm" , "it": "out"}, 2744 {"inst": "vqrdmlsh.s16-32 Vd, Vn, Vm" , "t32": "1111|11110|Vd'|sz|Vn|Vd|1100|Vn'|1|Vm'|1|Vm" , "it": "out"}, 2745 {"inst": "vqrdmlsh.s16 Dd, Dn, Dm<=07[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"}, 2746 {"inst": "vqrdmlsh.s16 Vd, Vn, Dm<=07[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|i:1|Vm:3" , "it": "out"}, 2747 {"inst": "vqrdmlsh.s32 Dd, Dn, Dm<=15[#i]" , "t32": "1110|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm" , "it": "out"}, 2748 {"inst": "vqrdmlsh.s32 Vd, Vn, Dm<=15[#i]" , "t32": "1111|11111|Vd'|sz|Vn|Vd|1111|Vn'|1|i:1|0|Vm" , "it": "out"} 2749 ]}, 2750 2751 {"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [ 2752 {"inst": "sha1c.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}, 2753 {"inst": "sha1h.32 Vd, Vn" , "a32": "1111|00111|Vd'|11|1001|Vd|0|0101|1|Vn'|0|Vn"}, 2754 {"inst": "sha1m.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}, 2755 {"inst": "sha1p.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}, 2756 {"inst": "sha1su0.32 Vx, Vn, Vm" , "a32": "1111|00100|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}, 2757 {"inst": "sha1su1.32 Vx, Vn" , "a32": "1111|00111|Vx'|11|1010|Vx|0|0111|0|Vn'|0|Vn"} 2758 ]}, 2759 2760 {"category": "ASIMD CRYPTO_HASH", "ext": "SHA1", "data": [ 2761 {"inst": "sha1c.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2762 {"inst": "sha1h.32 Vd, Vn" , "t32": "1111|11111|Vd'|11|1001|Vd|0|0101|1|Vn'|0|Vn" , "it": "out"}, 2763 {"inst": "sha1m.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2764 {"inst": "sha1p.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2765 {"inst": "sha1su0.32 Vx, Vn, Vm" , "t32": "1110|11110|Vx'|11|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2766 {"inst": "sha1su1.32 Vx, Vn" , "t32": "1111|11111|Vx'|11|1010|Vx|0|0111|0|Vn'|0|Vn" , "it": "out"} 2767 ]}, 2768 2769 {"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [ 2770 {"inst": "sha256h.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}, 2771 {"inst": "sha256h2.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"}, 2772 {"inst": "sha256su0.32 Vx, Vn" , "a32": "1111|00111|Vx'|11|1010|Vx|0|0111|1|Vn'|0|Vn"}, 2773 {"inst": "sha256su1.32 Vx, Vn, Vm" , "a32": "1111|00110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm"} 2774 ]}, 2775 2776 {"category": "ASIMD CRYPTO_HASH", "ext": "SHA256", "data": [ 2777 {"inst": "sha256h.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|00|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2778 {"inst": "sha256h2.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|01|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"}, 2779 {"inst": "sha256su0.32 Vx, Vn" , "t32": "1111|11111|Vx'|11|1010|Vx|0|0111|1|Vn'|0|Vn" , "it": "out"}, 2780 {"inst": "sha256su1.32 Vx, Vn, Vm" , "t32": "1111|11110|Vx'|10|Vn|Vx|1100|Vn'|1|Vm'|0|Vm" , "it": "out"} 2781 ]} 2782 ] 2783 }